R5F212B7SNFP#U0 Renesas Electronics America, R5F212B7SNFP#U0 Datasheet - Page 227

• Manufacturer Part Number: R5F212B7SNFP#U0
• Description: IC R8C/2B MCU FLASH 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Br

Specifications of R5F212B7SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 55
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2A Group, R8C/2B Group
Rev.2.00
REJ09B0324-0200
Figure 14.36
Timer RC Output Master Enable Register
b7 b6 b5 b4 b3 b2
NOTE:
1.
These bits are disabled for input pins set to the input capture function.
Nov 26, 2007
TRCOER Register
b1 b0
Bit Symbol
TRCOER
(b6-b4)
Symbol
PTO
EA
EB
EC
ED
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TRCIOA output disable bit
TRCIOB output disable bit
TRCIOC output disable bit
TRCIOD output disable bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
_____
INT0
cutoff signal input enabled
bit
of pulse output forced
Address
Bit Name
0132h
(1)
(1)
(1)
(1)
0 : Enable output
1 : Disable output (The TRCIOA pin is
0 : Enable output
1 : Disable output (The TRCIOB pin is
0 : Enable output
1 : Disable output (The TRCIOC pin is
0 : Enable output
1 : Disable output (The TRCIOD pin is
0 : Pulse output forced cutoff input disabled
1 : Pulse output forced cutoff input enabled
used as a programmable I/O port.)
used as a programmable I/O port.)
used as a programmable I/O port.)
used as a programmable I/O port.)
(Bits EA, EB, EC, and ED are set to 1
_____
INT0
(disable output) w hen “L” is applied to the
pin)
After Reset
01111111b
Function
14. Timers
RW
RW
RW
RW
RW
RW
—