MC9S12HZ128CAL Freescale Semiconductor, MC9S12HZ128CAL Datasheet
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MC9S12HZ256 Data Sheet Covers MC9S12HZ128, MC9S12HZ64, MC9S12HN64 MC3S12HZ256, MC3S12HZ128, MC3S12HZ64, MC3S12HN64, MC3S12HZ32 & MC3S12HN32 HCS12 Microcontrollers MC9S12HZ256V2 Rev. 2.05 04/2008 freescale.com ...
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MC9S12HZ256 Data Sheet MC9S12HZ256V2 Rev. 2.05 04/2008 ...
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... Added MC3S12HZ64 Pinout. Figure 1-7 April 25, 2008 02.05 Corrected register map typo. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2006. All rights reserved. 4 Description MC9S12HZ256 Data Sheet, Rev ...
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... Dual Output Voltage Regulator (VREG3V3V2 501 Chapter 18 Background Debug Module (BDMV4 509 Chapter 19 Debug Module (DBGV1 535 Chapter 20 Interrupt (INTV1 567 Chapter 21 Multiplexed External Bus Interface (MEBIV3 575 Chapter 22 Module Mapping Control (MMCV4 603 Freescale Semiconductor MC9S12HZ256 Data Sheet, Rev. 2.05 5 ...
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... Appendix A Electrical Characteristics 623 Appendix B PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 Appendix C Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658 Appendix D Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661 Appendix E ROM Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662 Appendix F Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666 Appendix G Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667 6 MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor ...
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... Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 1.10 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 1.10.1 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 1.10.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 1.10.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 256 Kbyte Flash Module (FTS256K2V1) 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Freescale Semiconductor Chapter 1 Chapter 2 MC9S12HZ256 Data Sheet, Rev. 2.05 7 ...
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... Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 3.4.1 Program and Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 3.5 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 3.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 3.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 3.5.3 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 3.6 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 3.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8 Chapter 3 MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor ...
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... RESET — Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 5.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 5.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 5.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Freescale Semiconductor Chapter 4 Chapter 5 — PLL Operating Voltage, PLL Ground . . . . . . . . . . . . . . . . . . . . . . 169 MC9S12HZ256 Data Sheet, Rev. 2.05 9 ...
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... External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 7.2.1 ANx (x = 15, 14, 13, 12, 11, 10 — Analog Input Channel x Pins 209 7.2.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0 — External Trigger Pins . . . . . . . . . . . . . . . . . 209 10 Chapter 6 Oscillator (OSCV2) — PLL Operating Voltage, PLL Ground . . . . . . . . . . . . . . . . . . . 204 Chapter 7 MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor ...
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... External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 9.2.1 M0C0M/M0C0P/M0C1M/M0C1P — PWM Output Pins for Motor 262 9.2.2 M1C0M/M1C0P/M1C1M/M1C1P — PWM Output Pins for Motor 262 9.2.3 M2C0M/M2C0P/M2C1M/M2C1P — PWM Output Pins for Motor 262 Freescale Semiconductor Chapter 8 Chapter 9 Motor Controller (MC10B8CV1) MC9S12HZ256 Data Sheet, Rev. 2.05 ...
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... Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 11.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 11.2.1 IIC_SCL — Serial Clock Line Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 11.2.2 IIC_SDA — Serial Data Line Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 12 Chapter 10 Stepper Stall Detector (SSDV1) Chapter 11 Inter-Integrated Circuit (IICV2) MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor ...
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... Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 12.4.4 Timer Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 12.4.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 12.4.6 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 12.4.7 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 12.4.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 12.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 12.5.1 MSCAN initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 Freescale Semiconductor Chapter 12 MC9S12HZ256 Data Sheet, Rev. 2.05 13 ...
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... Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 14.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 14.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 14.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 14.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 14.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 14.4.4 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 14 Chapter 13 Chapter 14 MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor ...
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... IOC7 — Input Capture and Output Compare Channel 7 Pin . . . . . . . . . . . . . . . . . . . . 478 16.2.2 IOC6 — Input Capture and Output Compare Channel 6 Pin . . . . . . . . . . . . . . . . . . . . 478 16.2.3 IOC5 — Input Capture and Output Compare Channel 5 Pin . . . . . . . . . . . . . . . . . . . . 478 16.2.4 IOC4 — Input Capture and Output Compare Channel 4 Pin . . . . . . . . . . . . . . . . . . . . 478 Freescale Semiconductor Chapter 15 Chapter 16 Timer Module (TIM16B8CV1) MC9S12HZ256 Data Sheet, Rev ...
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... Reduced-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 17.4.4 LVD — Low-Voltage Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 17.4.5 POR — Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 17.4.6 LVR — Low-Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 17.4.7 CTRL — Regulator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 17.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 16 Chapter 17 — Regulator Output2 (PLL 504 MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor ...
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... Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 19.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 19.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 19.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 19.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 Freescale Semiconductor Chapter 18 Chapter 19 Debug Module (DBGV1) MC9S12HZ256 Data Sheet, Rev. 2.05 17 ...
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... Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 21.4.1 Detecting Access Type from External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 21.4.2 Stretched Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597 21.4.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597 21.4.4 Internal Visibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 21.4.5 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 18 Chapter 20 Interrupt (INTV1) Chapter 21 MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor ...
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... A.4.2 Chip Power-up and Voltage Drops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 A.4.3 Output Loads 640 A.5 Reset, Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 A.5.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 A.5.2 Oscillator 643 A.5.3 Phase Locked Loop 644 A.6 MSCAN 648 A.7 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648 Freescale Semiconductor Chapter 22 Appendix A Electrical Characteristics MC9S12HZ256 Data Sheet, Rev. 2.05 19 ...
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... E.2.1 Security and Backdoor Key Access definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665 E.2.2 Unsecuring the MCU using the Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . 665 20 Appendix B PCB Layout Guidelines Appendix C Package Information Appendix D Derivative Differences Appendix E ROM Description Appendix F Ordering Information Appendix G Detailed Register Map MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor ...
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... Interrupt stacking and programmer’s model identical to M68HC11 16-bit ALU Instruction queue Enhanced indexed addressing – MEBI (multiplexed external bus interface) – MMC (module mapping control) – INT (interrupt control) – DBG (debugger and breakpoints) – BDM (background debug mode) Freescale Semiconductor MC9S12HZ256 Data Sheet, Rev. 2.05 21 ...
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... PWM motor controller (MC) with 16 high current drivers – Each PWM channel switchable between two drivers in an H-bridge configuration – Left, right and center aligned outputs – Support for sine and cosine drive – Dithering – Output slew rate control 22 MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor ...
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... Emulation expanded narrow mode • Special operating mode – Special single-chip mode with active background debug mode Low-power modes • Stop mode • Pseudo stop mode • Wait mode Freescale Semiconductor MC9S12HZ256 Data Sheet, Rev. 2.05 Chapter 1 MC9S12HZ256 Device Overview 23 ...
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... PWM4 M2COSP M2C0P SSD2 M2SINM M2C1M PWM5 M2SINP M2C1P M3COSM M3C0M PWM6 M3COSP M3C0P SSD3 M3SINM M3C1M PWM7 M3SINP M3C1P Freescale Semiconductor VDDA VSSA VRH VRL PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PP0 PP1 PP2 PP3 PP4 PP5 PM2 ...
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... Stepper Stall Detector 1 (SSD1) 0x0298–0x029F Stepper Stall Detector 2 (SSD2) 0x02A0–0x02A7 Stepper Stall Detector 3 (SSD3) 0x02A8–0x03FF Reserved Freescale Semiconductor Table 1-1. Device Register Map Overview Module MC9S12HZ256 Data Sheet, Rev. 2.05 Chapter 1 MC9S12HZ256 Device Overview Size (Bytes) 24 ...
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... See table below for mapping options 0x3FFF 0x4000 0.5K, 1K Protected Sector 16K Fixed Flash or ROM 0x7FFF 0x8000 16K Page Window Sixteen * 16K Flash or ROM Pages 0xBFFF 0xC000 16K Fixed Flash or ROM 2K, 4K 16K Protected Boot Sector 0xFFFF 0xFF00 BDM (If Active) 0xFFFF Freescale Semiconductor ...
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... User must initialize RAM13 bit to the same value as RAMHAL bit Freescale Semiconductor EXT VECTORS SPECIAL * Assuming that a ‘0’ was driven onto port K7 during reset to normal expanded mode ^ EEPROM is not available in ROM device SINGLE CHIP Figure 1-3. MC9(3)S12HZ128 Memory Map ...
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... Four * 16K Flash or ROM Pages 16K Fixed Flash or ROM 2K, 4K 16K Protected Boot Sector BDM (If Active) ^ EEPROM is not available in ROM devices Reserved location 0x1000 - 0x2FFF 0x1000 - 0x2FFF 0x5000 - 0x6FFF 0x5000 - 0x6FFF 0x9000 - 0xAFFF 0x9000 - 0xAFFF 0xD000 - 0xEFFF 0xD000 - 0xEFFF Freescale Semiconductor ...
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... Table 1-5. MC3S12HZ32 and MC3S12HN32 RAM mapping options 1 INITRM 0x00 0x39 0x40 0x79 0x80 0xB9 0xC0 0xF9 1 User must initialize RAM13, RAM12 and RAM11 bits to the same value as RAMHAL bit Freescale Semiconductor 0x0000 0x03FF 0x3800 0x3FFF 0x4000 0x7FFF 0x8000 0xBFFF 0xC000 0xFFFF 0xFF00 VECTORS ...
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... MC3S12HZ32 MC3S12HN32 30 Mask Set 2L16Y/3L16Y 0x1402/0x1403 1M36C shows the read-only values of these registers. Refer to the HCS12 MMC Table 1-7. Memory Size Registers MEMSIZ0 0x15 0x01 MC9S12HZ256 Data Sheet, Rev. 2.05 Table 1-6 shows the 1 Part ID 0x1501 MEMSIZ1 0x81 0x80 Freescale Semiconductor ...
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... The MC9S12HZ256 are available in a 112-pin quad flat pack (LQFP) and a 80-pin quad flat pack (QFP). Most pins perform two or more functions, as described in Figure 1-7 and Figure 1-8 show the pin assignments. Freescale Semiconductor 1.5, “Detailed Signal MC9S12HZ256 Data Sheet, Rev. 2.05 Chapter 1 MC9S12HZ256 Device Overview Descriptions”. Figure ...
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... MC9S12HZ256, MC9S12HZ128, MC3S12HZ256, MC3S12HZ128 112 LQFP MC9S12HZ256 Data Sheet, Rev. 2.05 84 PB5/ADDR5/DATA5/FP5 83 PB4/ADDR4/DATA4/FP4 82 PB3/ADDR3/DATA3/FP3 81 PB2/ADDR2/DATA2/FP2 80 PB1/ADDR1/DATA1/FP1 79 PB0/ADDR0/DATA0/FP0 78 PK0/XADDR14/BP0 77 PK1/XADDR15/BP1 76 PK2/XADDR16/BP2 75 PK3/XADDR17/BP3 74 VLCD 73 VSS1 72 VDD1 71 PAD7/KWAD7/AN7 70 PAD6/KWAD6/AN6 69 PAD5/KWAD5/AN5 68 PAD4/KWAD4/AN4 67 PAD3/KWAD3/AN3 66 PAD2/KWAD2/AN2 65 PAD1/KWAD1/AN1 64 PAD0/KWAD0/AN0 63 VDDA 62 VRH 61 VRL 60 VSSA 59 PE0/XIRQ 58 PE4/ECLK 57 PE6/IPIPE1/MODB Freescale Semiconductor ...
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... M3C1P/M1SINP/PV7 24 VDDM3 25 VSSM3 26 PWM5/PP5 27 PWM4/PP4 28 Figure 1-7. 112-Pin LQFP for MC9S12HZ(N)64 and MC3S12HZ(N)64 Freescale Semiconductor MC9S12HZ64, MC9S12HN64, MC3S12HZ64, MC3S12HN64 112 LQFP Signals shown in BOLD are not available in the 80 QFP package MC9S12HZ256 Data Sheet, Rev. 2.05 Chapter 1 MC9S12HZ256 Device Overview 84 PB5/FP5 83 PB4/FP4 ...
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... Figure 1-8. 80-Pin QFP for MC9S12HZ(N)64, MC3S12HZ(N)64 and MC3S12HZ(N)32 34 MC9S12HZ64, MC9S12HN64, MC3S12HZ64, MC3S12HN64, MC3S12HZ32, MC3S12HN32 80 QFP MC9S12HZ256 Data Sheet, Rev. 2.05 60 PB5/FP5 59 PB4/FP4 58 PK0/BP0 57 PK1/BP1 56 PK2/BP2 55 PK3/BP3 54 VLCD 53 VSS1 52 VDD1 51 PAD6/KWAD6/AN6 50 PAD5/KWAD5/AN5 49 PAD4/KWAD4/AN4 48 PAD3/KWAD3/AN3 47 PAD2/KWAD2/AN2 46 PAD1/KWAD1/AN1 45 PAD0/KWAD0/AN0 44 VDDA/VRH 43 VSSA/VRL 42 PE0/XIRQ 41 PE4/ECLK Freescale Semiconductor ...
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... PE2 FP20 R/W PE1 IRQ — PE0 XIRQ — PK7 FP23 ECS PK[3:0] BP[3:0] XADDR[17:14] PL[7:4] FP[31:28] AN[15:12] PL[3:0] FP[19:16] AN[11:8] Freescale Semiconductor Table 1-8. Signal Properties Internal Pull Up Pin Resistor Powered Name by Function 4 CTRL — DDPLL — DDPLL — V None DDX2 — ...
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... Port S I/O, RXD of SCI0 Down Port T I/O, Timer channels Port T I/O, Timer channels, LCD driver Disabled Port U I/O, motor1 coil nodes SSD1 Port U I/O, motor 0 coil nodes SSD0 Disabled Port V I/O, motor 3 coil nodes SSD3 Port V I/O, motor 2 coil nodes SSD2 Freescale Semiconductor ...
Page 37
... RESET — External Reset Pin An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset. Freescale Semiconductor Table 1-9. Power and Ground Description /V voltages and bypass the internal voltage regulator. ...
Page 38
... PA7–PA0 are general-purpose input or output pins. They can be configured as frontplane segment driver outputs FP15–FP8 of the LCD. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus. 38 NOTE in all applications. SS XFC R MCU DDPLL Figure 1-9. PLL Loop Filter Connections MC9S12HZ256 Data Sheet, Rev. 2. DDPLL Freescale Semiconductor ...
Page 39
... DC voltage bias is applied to the crystal. Please contact the crystal manufacturer for crystal DC. Figure 1-10. Colpitts Oscillator Connections (PE7 = 0) EXTAL MCU XTAL * Rs can be zero (shorted) when use with higher frequency crystals. Refer to manufacturer’s data. Figure 1-11. Pierce Oscillator Connections (PE7 = 1) Freescale Semiconductor CDC SSPLL ...
Page 40
... PE0 / XIRQ — Port E Input Pin 0 PE0 is a general-purpose input pin and also the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This can wake up the MCU from stop or wait mode. 40 MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor ...
Page 41
... PM3 / TXCAN0 — Port M I/O Pin 3 PM3 is a general-purpose input or output pin. It can be configured as the transmit pin TXCAN0 of the scalable controller area network controller 0 (CAN0) Freescale Semiconductor MC9S12HZ256 Data Sheet, Rev. 2.05 Chapter 1 MC9S12HZ256 Device Overview 41 ...
Page 42
... PS7 is a general-purpose input or output pin. It can be configured as slave select pin SS of the serial peripheral interface (SPI). 1.5.6.27 PS6 / SCK — Port S I/O Pin 6 PS6 is a general-purpose input or output pin. It can be configured as serial clock pin SCK of the serial peripheral interface (SPI). 42 MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor ...
Page 43
... PU3–PU0 are general-purpose input or output pins. They can be configured as high current PWM output pins which can be used for motor drive or to measure the back EMF to calibrate the pointer reset position. These pins interface to the coils of motor 0. Freescale Semiconductor MC9S12HZ256 Data Sheet, Rev. 2.05 Chapter 1 MC9S12HZ256 Device Overview ...
Page 44
... External Power and Ground Pins SSX1 SSX2 are the power supply and ground pins for input/output drivers.V are not internally connected. SSX2 — Internal Logic Power Pins NOTE MC9S12HZ256 Data Sheet, Rev. 2.05 (Table B-1). and V are internally connected. SS1 SS2 Freescale Semiconductor DDX1 ...
Page 45
... V are the PLL supply pins and serve as connection points for external loop filter DDPLL SSPLL components. No load allowed except for bypass capacitors. Freescale Semiconductor , V — Power Supply Pins for Motor DDM3 — Ground Pins for Motor SSM3 — Power Supply Pins for PLL NOTE MC9S12HZ256 Data Sheet, Rev ...
Page 46
... Figure 1-12. Clock Connections MC9S12HZ256 Data Sheet, Rev. 2.05 HCS12 CORE BDM CPU MEBI MMC INT DBG Flash RAM EEPROM TIM ATD PWM SCI0, SCI1 SPI CAN0, CAN1 IIC MC LCD PIM SSD1, SSD2, SSD3, SSD4 Freescale Semiconductor ...
Page 47
... The following paragraphs discuss the default bus setup and describe which aspects of the bus can be changed after reset on a per mode basis. Freescale Semiconductor Table 1-10. Mode Selection Mode Description Special Single Chip, BDM allowed and ACTIVE ...
Page 48
... The port E bit 3 pin can be reconfigured as the LSTRB bus control signal by writing “1” to the LSTRE bit in PEAR. The default condition of this pin is a general-purpose input because the LSTRB function is not needed in all expanded wide applications. 48 MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor ...
Page 49
... During cycles when the BDM is selected, R/W will remain high, data will maintain its previous state, and address and LSTRB pins will be updated with the internal value. During CPU no access cycles when the Freescale Semiconductor MC9S12HZ256 Data Sheet, Rev. 2.05 Chapter 1 MC9S12HZ256 Device Overview ...
Page 50
... MCU was reset. There is no external expansion bus after reset in this mode. Ports A and B are initially simple bidirectional I/O pins that are configured as high-impedance inputs with internal pull-downs enabled; however, writing 50 MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor ...
Page 51
... This will be the most common usage of the secured part. Everything will appear the same as if the part was not secured with the exception of BDM operation. The BDM operation will be blocked. Freescale Semiconductor MC9S12HZ256 Data Sheet, Rev. 2.05 Chapter 1 MC9S12HZ256 Device Overview ...
Page 52
... COP failure reset None None SWI None XIRQ X-Bit MC9S12HZ256 Data Sheet, Rev. 2.05 Table 1-11. System resets can HPRIO Value Local Enable to Elevate None — COPCTL (CME, FCME) — COP rate select — None — None — None — Freescale Semiconductor ...
Page 53
... Freescale Semiconductor CCR Interrupt Source Mask IRQ I-Bit Real Time Interrupt I-Bit Timer channel 0 I-Bit Timer channel 1 I-Bit ...
Page 54
... Reserved 0xA2 MDC0CTL (MCZIE, AOVIE) 0xA0 MDC1CTL (MCZIE, AOVIE) 0x9E MDC2CTL (MCZIE, AOVIE) 0x9C MDC3CTL (MCZIE, AOVIE) 0x9A Reserved 0x98 MCCTL1 (MCOCIE) 0x96 Reserved 0x94 Reserved 0x92 Reserved 0x90 Reserved 0x8E PWMSDN(PWMIE) 0x8C VREGCTRL (LVIE) 0x8A Reserved 0x80–0x88 Freescale Semiconductor ...
Page 55
... Refer to the PIM block description chapter for reset configurations of all peripheral module ports. Refer to Table 1-1 for locations of the memories depending on the operating mode after reset. The RAM array is not automatically initialized out of reset. Freescale Semiconductor Table 1-12. The different sources capable of generating a Table 1-12. ...
Page 56
... Chapter 1 MC9S12HZ256 Device Overview 56 MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor ...
Page 57
... Fast sector erase and word program operation • 2-stage command pipeline for faster multi-word program times • Sector erase abort feature for critical interrupt response • Flexible protection scheme to prevent accidental program or erase Freescale Semiconductor CAUTION MC9S12HZ256 Data Sheet, Rev. 2.05 57 ...
Page 58
... Code integrity check using built-in data compression 2.1.3 Modes of Operation Program, erase, erase verify, and data compress operations (please refer to 2.1.4 Block Diagram A block diagram of the Flash module is shown in 58 Figure 2-1. MC9S12HZ256 Data Sheet, Rev. 2.05 Section 2.4.1 for details). Freescale Semiconductor ...
Page 59
... Divider 2.2 External Signal Description The Flash module contains no signals that connect off-chip. 2.3 Memory Map and Register Definition This subsection describes the memory map and registers for the Flash module. Freescale Semiconductor Command Interface Common Registers Banked Registers Command Pipelines ...
Page 60
... Status Register (FSTAT)” 1 Refer to Section 2.3.2.9, “Flash Control Register (FCTL)” 1 Refer to Section 2.3.2.2, “Flash Security Register (FSEC)” MC9S12HZ256 Data Sheet, Rev. 2.05 (FPROT)”, can be set to Description Backdoor Comparison Key Access” Reserved Flash Nonvolatile Byte Flash Security Byte Freescale Semiconductor ...
Page 61
... FLASH_START = 0x4000 0x4400 0x4800 0x5000 0x6000 0x8000 Flash Blocks 0xC000 0xE000 0xF000 0xF800 FLASH_END = 0xFFFF Note: 0x30–0x3F correspond to the PPAGE register content Freescale Semiconductor (16 bytes) Flash Registers Flash Protected Low Sectors Kbytes 0x3E 16K PAGED MEMORY 0x38 0x39 0x3A 0x3B Block 0 ...
Page 62
... Block Relative 1 Block Address 0 0x018000–0x01BFFF 1 0x000000–0x003FFF 0x004000–0x007FFF 0x008000–0x00BFFF 0x00C000–0x00FFFF 0x010000–0x013FFF 0x014000–0x017FFF 0x018000–0x01BFFF 0x01C000–0x01FFFF 0 0x000000–0x003FFF 0x004000–0x007FFF 0x008000–0x00BFFF 0x00C000–0x00FFFF 0x010000–0x013FFF 0x014000–0x017FFF 0x018000–0x01BFFF 0x01C000–0x01FFFF 0 0x01C000–0x01FFFF Freescale Semiconductor ...
Page 63
... Flash Low Data Register (FDATALO) 0x000C RESERVED1 0x000D RESERVED2 0x000E RESERVED3 0x000F RESERVED4 1 Intended for factory test purposes only. Freescale Semiconductor Chapter 2 256 Kbyte Flash Module (FTS256K2V1) Section 2.3.2, “Register Table 2-3. Flash Register Map Register Name MC9S12HZ256 Data Sheet, Rev. 2.05 ...
Page 64
... FPHS CCIF PVIOL ACCERR NV6 NV5 NV4 FADDRHI FADDRLO FDATAHI FDATALO Unimplemented or Reserved Figure 2-3. FTS256K2 Register Summary MC9S12HZ256 Data Sheet, Rev. 2. FDIV3 FDIV2 FDIV1 FDIV0 RNV3 RNV2 SEC BKSEL FPLDIS FPLS 0 BLANK 0 CMDB NV3 NV2 NV1 Freescale Semiconductor Bit NV0 0 ...
Page 65
... The maximum divide ratio is 512. Please refer to FCLKDIV Register” for more information. 2.3.2.2 Flash Security Register (FSEC) The unbanked FSEC register holds all bits associated with the security of the MCU and Flash module. Freescale Semiconductor ...
Page 66
... Table 2-6. Flash KEYEN States Status of Backdoor Key Access 00 DISABLED 1 01 DISABLED 10 ENABLED 11 DISABLED Table 2-7. Flash Security States Status of Security 00 SECURED 1 01 SECURED 10 UNSECURED 11 SECURED Section 2.6, “Flash Module MC9S12HZ256 Data Sheet, Rev. 2. RNV2 SEC Table 2-7. If the Flash Security”. Freescale Semiconductor ...
Page 67
... CBEIE CCIE W Reset Unimplemented or Reserved Figure 2-7. Flash Configuration Register (FCNFG) CBEIE, CCIE, KEYACC and BKSEL bits are readable and writable while all remaining bits read 0 and are not writable. KEYACC is only writable if KEYEN (see Freescale Semiconductor WRALL Table 2-8. FTSTMOD Field Descriptions ...
Page 68
... Section 2.3.2.7, “Flash Status Register (FSTAT)”) Section 2.3.2.7, “Flash Status Register FPHDIS FPHS Restrictions”). Table 2-10. Reset Loading of FPROT Flash Address Protection Byte for 0xFF0D Flash Block 0 0xFF0C Flash Block 1 MC9S12HZ256 Data Sheet, Rev. 2.05 (FSTAT)” FPLDIS FPLS Freescale Semiconductor ...
Page 69
... For range sizes, refer to Freescale Semiconductor Table 2-11. FPROT Field Descriptions Description 2-13. The FPHS[1:0] bits can only be written to while the FPHDIS bit is set. 2-14. The FPLS[1:0] bits can only be written to while the FPLDIS bit is set. Table 2-12. Flash Protection Function ...
Page 70
... Paged Address Range 0x0036/0x003E: 0x8000–0x83FF 0x0036/0x003E: 0x8000–0x87FF 0x0036/0x003E: 0x8000–0x8FFF 0x0036/0x003E: 0x8000–0x9FFF Figure 2-9. Although the protection scheme is MC9S12HZ256 Data Sheet, Rev. 2.05 Protected Size 2 Kbytes 4 Kbytes 8 Kbytes 16 Kbytes Protected Size 1 Kbyte 2 Kbytes 4 Kbytes 8 Kbytes Freescale Semiconductor ...
Page 71
... The general guideline is that Flash protection can only be added and not removed. valid transitions between Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored and the FPROT register will remain unchanged. The contents of the Freescale Semiconductor FPHDIS = 1 FPHDIS = 0 ...
Page 72
... CBEIF, PVIOL, and ACCERR are readable and writable, CCIF and BLANK are readable and not writable, remaining bits read 0and are not writable in normal mode. FAIL is readable and writable in special mode. FAIL must be clear when starting a command write sequence Protection Scenario PVIOL ACCERR PVIOL ACCERR MC9S12HZ256 Data Sheet, Rev. 2. BLANK BLANK 0 FAIL Freescale Semiconductor ...
Page 73
... Flash operation completed without error. 1 Flash operation failed. 2.3.2.8 Flash Command Register (FCMD) The banked FCMD register is the Flash command register. Freescale Semiconductor Table 2-16. FSTAT Field Descriptions Description MC9S12HZ256 Data Sheet, Rev. 2.05 Chapter 2 256 Kbyte Flash Module (FTS256K2V1) Figure 2-29) ...
Page 74
... Sector Erase 0x41 Mass Erase 0x47 Sector Erase Abort NV5 NV4 NV3 Figure 2-13. Flash Control Register (FCTL) Table 2-19. FCTL Field Descriptions Description MC9S12HZ256 Data Sheet, Rev. 2. 2-18. Writing any command other than those 2 1 NV2 NV1 F F Freescale Semiconductor NV0 F ...
Page 75
... The banked FDATAHI and FDATALO registers are the Flash data registers Reset Unimplemented or Reserved Figure 2-16. Flash Data High Register (FDATAHI Reset Unimplemented or Reserved Figure 2-17. Flash Data Low Register (FDATALO) Freescale Semiconductor Chapter 2 256 Kbyte Flash Module (FTS256K2V1 FADDRHI FADDRLO ...
Page 76
... All bits read 0 and are not writable. 2.3.2.14 RESERVED3 This register is reserved for factory testing and is not accessible Reset Unimplemented or Reserved All bits read 0 and are not writable Figure 2-18. RESERVED1 Figure 2-19. RESERVED2 Figure 2-20. RESERVED3 MC9S12HZ256 Data Sheet, Rev. 2. Freescale Semiconductor ...
Page 77
... Because the program and erase timings are also a function of the bus clock, the FCLKDIV determination must take this information into account define: • FCLK as the clock of the Flash timing control block, • Tbus as the period of the bus clock, and Freescale Semiconductor Chapter 2 256 Kbyte Flash Module (FTS256K2V1 ...
Page 78
... If the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not been written since the last reset. Flash commands will not be executed if the FCLKDIV register has not been written to. 78 200 190 200 100 5% – = CAUTION MC9S12HZ256 Data Sheet, Rev. 2.05 Figure 2-22. Freescale Semiconductor ...
Page 79
... FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[ s])-1 TRY TO DECREASE Tbus YES Figure 2-22. Determination Procedure for PRDIV8 and FDIV Bits Freescale Semiconductor START NO Tbus < ALL COMMANDS IMPOSSIBLE YES PRDIV8=0 (reset) OSCILLATOR NO CLOCK > 12.8 MHZ? YES PRDIV8=1 PRDCLK=oscillator_clock PRDCLK=oscillator_clock/8 NO PRDCLK[MHz]*(5+Tbus[ s]) an integer? FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[ s])) ...
Page 80
... Section 2.4.1.3.4, “Sector Erase Section 2.4.1.3.5, “Mass Erase Section 2.4.1.3.6, “Sector Erase Abort MC9S12HZ256 Data Sheet, Rev. 2.05 Command”), the contents Command”), the Command”), the contents of the Command”), the contents Command”), the contents of Command”), Freescale Semiconductor ...
Page 81
... The Flash sector must not be considered erased if the ACCERR flag is set upon Abort command completion. A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed. Freescale Semiconductor Chapter 2 256 Kbyte Flash Module (FTS256K2V1) Function on Flash Memory CAUTION MC9S12HZ256 Data Sheet, Rev. 2.05 ...
Page 82
... Read: Register FSTAT Bit yes Write: Register FSTAT ACCERR Clear bit ACCERR 0x10 Set? no Bit no CCIF Read: Register FSTAT Set? yes Bit no Flash Block Not Erased; BLANK Mass Erase Flash Block Set? yes EXIT MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor ...
Page 83
... Flash sector must be erased using the sector erase command and then reprogrammed using the program command. The data compress command can be used to verify that a sector or sequential set of sectors are erased. Freescale Semiconductor Chapter 2 256 Kbyte Flash Module (FTS256K2V1) NOTE MC9S12HZ256 Data Sheet, Rev ...
Page 84
... Bit yes Write: Register FSTAT ACCERR Clear bit ACCERR 0x10 Set? no Bit no CCIF Set? yes Read: Register FDATA Data Compress Signature no Signature Valid? Flash Region Compressed yes EXIT MC9S12HZ256 Data Sheet, Rev. 2.05 Read: Register FSTAT Erase and Reprogram Freescale Semiconductor ...
Page 85
... Error Check Address, Data, Command Buffer Empty Check Bit Polling for Command Completion Check Figure 2-25. Example Program Command Flow Freescale Semiconductor no Write: Register FCLKDIV NOTE: command write sequence aborted by writing 0x00 to FSTAT register. NOTE: command write sequence aborted by writing 0x00 to FSTAT register ...
Page 86
... Write: Register FSTAT PVIOL Clear bit PVIOL 0x20 Set? no Bit yes Write: Register FSTAT ACCERR Clear bit ACCERR 0x10 Set? no Bit yes CBEIF Set? no Bit no CCIF Read: Register FSTAT Set? yes EXIT MC9S12HZ256 Data Sheet, Rev. 2.05 yes Next Write? no Freescale Semiconductor ...
Page 87
... Error Check Address, Data, Command Buffer Empty Check Bit Polling for Command Completion Check Figure 2-27. Example Mass Erase Command Flow Freescale Semiconductor no Write: Register FCLKDIV NOTE: command write sequence aborted by writing 0x00 to FSTAT register. NOTE: command write sequence aborted by writing 0x00 to FSTAT register ...
Page 88
... ACCERR flag, if set. The sector erase abort command must be used sparingly because a sector erase operation that is aborted counts as a complete program/erase cycle. 88 NOTE NOTE MC9S12HZ256 Data Sheet, Rev. 2.05 Section 2.4.1.1, “Writing the Freescale Semiconductor ...
Page 89
... Bit Polling for Command Completion Check NOTE: command write sequence aborted by writing 0x00 to FSTAT register. NOTE: command write sequence aborted by writing 0x00 to FSTAT register. Figure 2-28. Example Sector Erase Abort Command Flow Freescale Semiconductor Bit Erase no CCIF Abort Set? Needed? yes yes ...
Page 90
... Writing the sector erase command if the address written in the command write sequence was in a protected area of the Flash memory. 3. Writing the mass erase command while any Flash protection is enabled. 90 Section 2.4.1.3.6, “Sector Erase Abort Section 2.3.2.7, “Flash Status Register MC9S12HZ256 Data Sheet, Rev. 2.05 Section 2.5.2, “Stop Mode”). (FSTAT)”). Freescale Semiconductor ...
Page 91
... MCU is unsecured and the higher address sector is unprotected. If the Flash security byte remains in a secured state, any reset will cause the MCU to initialize to a secure operating mode. Freescale Semiconductor Chapter 2 256 Kbyte Flash Module (FTS256K2V1) Sequence”). ...
Page 92
... The backdoor keys stored in addresses 0xFF00–0xFF07 are unaffected by the backdoor key access sequence. After the next reset of the MCU, the security state of the Flash module 92 Section 2.3.2.2, “Flash Security Register Section 2.3.2.2, “Flash Security Register MC9S12HZ256 Data Sheet, Rev. 2.05 (FSEC)”) and the (FSEC)”), Freescale Semiconductor ...
Page 93
... Interrupts The Flash module can generate an interrupt when all Flash command operations have completed, when the Flash address, data, and command buffers are empty. Freescale Semiconductor Chapter 2 256 Kbyte Flash Module (FTS256K2V1) Table 2-1: Section 2 ...
Page 94
... CCIF (FSTAT register) NOTE Figure 2-29. CBEIE CCIE Figure 2-29. Flash Interrupt Implementation Section 2.3.2.4, “Flash Configuration Register (FSTAT)”. MC9S12HZ256 Data Sheet, Rev. 2.05 Local Enable Global (CCR) Mask I Bit CCIE (FCNFG register) I Bit Flash Command Interrupt Request Freescale Semiconductor ...
Page 95
... Interrupts on EEPROM command completion and command buffer empty • Fast sector erase and word program operation • 2-stage command pipeline • Flexible protection scheme for protection against accidental program or erase • Single power supply program and erase Freescale Semiconductor CAUTION MC9S12HZ256 Data Sheet, Rev. 2.05 95 ...
Page 96
... A description of this protection/reserved field is given in 96 Section 3.4.1 for details). EEPROM Array 1024 * 16 Bits row0 row1 row1023 comm1 addr1 data1 EECLK Figure 3-1. EETS2K Block Diagram MC9S12HZ256 Data Sheet, Rev. 2.05 Command Complete Interrupt Command Buffer Empty Interrupt Table 3-1. Freescale Semiconductor ...
Page 97
... MODULE BASE + 0x0000 MODULE BASE + 0x000B EEPROM BASE + 0x0000 1536 BYTES 0x0600 0x0640 0x0680 0x06C0 0x0700 0x0740 0x0780 0x07C0 EEPROM BASE + 0x07FF Freescale Semiconductor Size Description (Bytes) 13 Reserved 1 EEPROM protection byte 2 Reserved (12 BYTES) EEPROM Registers EEPROM ARRAY EEPROM Protected High Sectors 64, 128, 192, 256, 320, 384, 448, 512 bytes 0x07F0 – ...
Page 98
... EEPROM High Data Register (EDATAHI) 0x000B EEPROM Low Data Register (EDATALO) 1 Intended for factory test purposes only. 98 Table 3-2. EEPROM Register Map Register Name MC9S12HZ256 Data Sheet, Rev. 2.05 Normal Mode Access R R/W R/W R/W R/W R R/W R/W R/W R/W Freescale Semiconductor ...
Page 99
... CBEIF W ECMD RESERVED3 EADDRHI EADDRLO R W EDATAHI R W EDATALO R W 3.3.2.1 EEPROM Clock Divider Register (ECLKDIV) The ECLKDIV register is used to control timed events in program and erase algorithms. Freescale Semiconductor PRDIV8 EDIV5 EDIV4 CCIE NV6 NV5 NV4 CCIF PVIOL ACCERR 0 CMDB6 CMDB5 0 ...
Page 100
... This register is reserved for factory testing and is not accessible to the user Reset Unimplemented or Reserved 100 EDIV5 EDIV4 EDIV3 Table 3-3. ECLKDIV Field Descriptions Description Figure 3-5. RESERVED1 Figure 3-6. RESERVED2 MC9S12HZ256 Data Sheet, Rev. 2. EDIV2 EDIV1 EDIV0 Section 3.4.1.1, “Writing the Freescale Semiconductor ...
Page 101
... All bits in the EPROT register are readable. Bits NV[6:4] are not writable. The EPOPEN and EPDIS bits in the EPROT register can only be written to the protected state (i.e., 0). The EP[2:0] bits can be written anytime until bit EPDIS is cleared. If the EPOPEN bit is cleared, then the state of the EPDIS and EP[2:0] bits is irrelevant. Freescale Semiconductor ...
Page 102
... Protected Size Address Range 000 0x07C0-0x07FF 001 0x0780-0x07FF 128 bytes 010 0x0740-0x07FF 192 bytes 011 0x0700-0x07FF 256 bytes 100 0x06C0-0x07FF 320 bytes 101 0x0680-0x07FF 384 bytes 110 0x0640-0x07FF 448 bytes 111 0x0600-0x07FF 512 bytes MC9S12HZ256 Data Sheet, Rev. 2.05 64 bytes Freescale Semiconductor ...
Page 103
... Protection Violation — The PVIOL flag indicates an attempt was made to program or erase an address in a PVIOL protected EEPROM memory area writing PVIOL. Writing the PVIOL flag has no effect on PVIOL. While PVIOL is set not possible to launch another command in the EEPROM failure 1 A protection violation has occurred Freescale Semiconductor PVIOL ACCERR ...
Page 104
... Description Operations). This can be either a violation of the command sequence, issuing CMDB5 Table 3-8. ECMD Field Descriptions Description sets the ACCERR bit in the ESTAT register. MC9S12HZ256 Data Sheet, Rev. 2. CMDB2 CMDB0 0 0 Table 3-9. Any other command written than Freescale Semiconductor 0 0 ...
Page 105
... In normal modes, all EADDRHI and EADDRLO bits read 0 and are not writable. In special modes, all EADDRHI and EADDRLO bits are readable and writable except EADDRHI[7:2] which are not writable and always read 0. Freescale Semiconductor Table 3-9. Valid EEPROM Command List Command ...
Page 106
... Chapter 3 2 Kbyte EEPROM Module (EETS2KV1) For sector erase, the MCU address bits AB[1:0] are ignored. For mass erase, any address within the block is valid to start the command. 106 MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor ...
Page 107
... Writing the ECLKDIV Register Prior to issuing any program or erase command first necessary to write the ECLKDIV register to divide the oscillator down to within 150 kHz to 200 kHz range. The program and erase timings are also a Freescale Semiconductor Chapter 3 2 Kbyte EEPROM Module (EETS2KV1) 5 ...
Page 108
... If the ECLKDIV register is written, the bit EDIVLD is set automatically. If this bit is 0, the register has not been written since the last reset. EEPROM commands will not be executed if this register has not been written to. 108 Figure 3-17. 200 190 – 200 100 = 5% CAUTION MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor ...
Page 109
... EDIV[5:0] = PRDCLK[MHz]*(5+Tbus[ s])-1 TRY TO DECREASE Tbus YES Figure 3-17. PRDIV8 and EDIV Bits Determination Procedure Freescale Semiconductor START NO Tbus 1 s? PROGRAM/ERASE IMPOSSIBLE yes PRDIV8 = 0 (reset) OSCILLATOR NO CLOCK > 12.8 MHz? yes PRDIV8 = 1 PRDCLK = oscillator clock PRDCLK = oscillator clock/8 NO PRDCLK[MHz]*(5+Tbus[ s]) ...
Page 110
... ACCERR flag. A summary of the launching of a program operation is shown in writes the appropriate command to the ECMD register. 110 Table 3-10, to the ECMD register. Figure MC9S12HZ256 Data Sheet, Rev. 2.05 3-18. For other operations, the user Freescale Semiconductor ...
Page 111
... Error Check Address, Data, Command Buffer Empty Check Bit Polling for Command Completion Check Figure 3-18. Example Program Command Flow Freescale Semiconductor no Write: Register ECLKDIV NOTE: command sequence aborted by writing 0x00 to ESTAT register. NOTE: command sequence aborted by writing 0x00 to ESTAT register. ...
Page 112
... Writing an invalid command to the ECMD register in normal mode. 8. Writing to any EEPROM register other than ESTAT (to clear CBEIF) after writing to the command register (ECMD). 112 Table 3-10. Valid EEPROM Commands Function on EEPROM Array CAUTION MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor ...
Page 113
... As active commands are immediately aborted when the MCU enters stop mode strongly recommended that the user does not use the STOP instruction during program, erase, or sector modify operations. Freescale Semiconductor Chapter 3 2 Kbyte EEPROM Module (EETS2KV1) NOTE MC9S12HZ256 Data Sheet, Rev. 2.05 Section 3 ...
Page 114
... If the chip is secured in special single-chip Table 3-11. EEPROM Interrupt Sources Interrupt Flag CBEIF (ESTAT register) CCIF (ESTAT register) NOTE Section 3.3.2.4, “EEPROM Configuration Register (ESTAT)”. MC9S12HZ256 Data Sheet, Rev. 2.05 Local Enable Global (CCR) Mask CBEIE I Bit CCIE I Bit Freescale Semiconductor ...
Page 115
... Input with selectable pull-up or pull-down device Optional features: • Open drain for wired-OR connections • Interrupt input with glitch filtering Freescale Semiconductor NOTE MC9S12HZ256 Data Sheet, Rev. 2.05 115 ...
Page 116
... PV0 M2C0P PV1 M2C1M PV2 M2C1P PV3 PV4 M3C0M PV5 M3C0P PV6 M3C1M PV7 M3C1P AN0 KWAD0 PAD0 AN1 KWAD1 PAD1 AN2 KWAD2 PAD2 AN3 KWAD3 PAD3 AN4 KWAD4 PAD4 AN5 KWAD5 PAD5 AN6 KWAD6 PAD6 AN7 KWAD7 PAD7 Freescale Semiconductor ...
Page 117
... R/W/GPIO PE1 IRQ GPIO PE0 XIRQ GPIO Freescale Semiconductor Chapter 4 Port Integration Module (PIM9HZ256V2) Description Refer to the MEBI block description chapter Refer to the BDM block description chapter Refer to the MEBI block description chapter Refer to the MEBI block description chapter LCD driver interface ...
Page 118
... Refer to the MEBI block description chapter LCD driver interface General-purpose I/O Refer to the MEBI block description chapter LCD driver interface General-purpose I/O MC9S12HZ256 Data Sheet, Rev. 2.05 Pin Function after Reset Refer to the MEBI block description chapter Refer to the MEBI block description chapter Freescale Semiconductor ...
Page 119
... AN10 GPIO PL1 FP17 AN9 GPIO PL0 FP16 AN8 GPIO Freescale Semiconductor Chapter 4 Port Integration Module (PIM9HZ256V2) Description Analog-to-digital converter input channel 7 Keyboard wake-up interrupt 7 General-purpose I/O Analog-to-digital converter input channel 6 Keyboard wake-up interrupt 6 General-purpose I/O Analog-to-digital converter input channel 5 Keyboard wake-up interrupt 5 ...
Page 120
... Serial peripheral interface master out/slave in pin General-purpose I/O Serial peripheral interface master in/slave out pin General-purpose I/O Serial communication interface 0 transmit pin General-purpose I/O Serial communication interface 0 receive pin General-purpose I/O MC9S12HZ256 Data Sheet, Rev. 2.05 Pin Function after Reset GPIO GPIO GPIO Freescale Semiconductor ...
Page 121
... PU2 M0SINM M0C1M GPIO PU1 M0COSP M0C0P GPIO PU0 M0COSM M0C0M GPIO Freescale Semiconductor Chapter 4 Port Integration Module (PIM9HZ256V2) Description Timer channel 7 General-purpose I/O Timer channel 6 General-purpose I/O Timer channel 5 General-purpose I/O Timer channel 4 General-purpose I/O LCD driver interface Timer channel 3 ...
Page 122
... General-purpose I/O SSD2 sine- node PWM motor controller channel 5 General-purpose I/O SSD2 cosine+ node PWM motor controller channel 4 General-purpose I/O SSD2 cosine- node PWM motor controller channel 4 General-purpose I/O MC9S12HZ256 Data Sheet, Rev. 2.05 Pin Function after Reset GPIO Freescale Semiconductor ...
Page 123
... Port P Pull Device Enable Register (PERP) 0x001D Port P Polarity Select Register (PPSP) 0x001E Port P Wired-OR Mode Register (WOMP) 0x001F - 0x002F Reserved Freescale Semiconductor Chapter 4 Port Integration Module (PIM9HZ256V2) Table 4-2 Table 4-2. PIM9HZ256 Memory Map Use MC9S12HZ256 Data Sheet, Rev. 2. standard memory map of port ...
Page 124
... MC9S12HZ256 Data Sheet, Rev. 2.05 Access R/W R R/W R/W R/W R/W — R/W R R/W R/W R/W R/W — R/W R R/W R/W R/W R/W — R/W — R — R/W — R/W — R/W — R/W — R/W — R/W — Freescale Semiconductor ...
Page 125
... I/O register bit (PTADx) reads “1”. If the associated data direction bit (DDRADx) is set to 0 (input) and the associated ATDDIEN1 bits is set to 1 (digital input buffer is enabled), a read returns the value of the pin. Freescale Semiconductor 5 4 ...
Page 126
... Associated pin is configured as input. 1 Associated pin is configured as output. 126 PTIAD5 PTIAD4 PTIAD3 Figure 4-3. Port AD Input Register (PTIAD DDRAD5 DDRAD4 DDRAD3 Table 4-3. DDRAD Field Descriptions Description MC9S12HZ256 Data Sheet, Rev. 2. PTIAD2 PTIAD1 PTIAD0 DDRAD2 DDRAD1 DDRAD0 Freescale Semiconductor ...
Page 127
... This register configures whether a pull- pull-down device is activated on configured input pins pin is configured as output, the corresponding Pull Device Enable Register bit has no effect. Field 7:0 Pull Device Enable Port AD PERAD[7:0] 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled. Freescale Semiconductor RDRAD5 RDRAD4 RDRAD3 0 ...
Page 128
... Interrupt Enable Port AD PIEAD[7:0] 0 Interrupt is disabled (interrupt flag masked). 1 Interrupt is enabled. 128 PPSAD5 PPSAD4 PPSAD3 Table 4-6. PPSAD Field Descriptions Description PIEAD5 PIEAD4 PIEAD3 Table 4-7. PIEAD Field Descriptions Description MC9S12HZ256 Data Sheet, Rev. 2. PPSAD2 PPSAD1 PPSAD0 PIEAD2 PIEAD1 PIEAD0 Freescale Semiconductor ...
Page 129
... Interrupt Flags Port AD PIFAD[7: active edge pending. Writing a “0” has no effect. 1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). Writing a “1” clears the associated flag. Freescale Semiconductor Chapter 4 Port Integration Module (PIM9HZ256V2 ...
Page 130
... LCD frontplane driver is disabled (or LCD module is disabled), a read returns the value of the pin. 130 PTL5 PTL4 PTL3 AN13 AN12 AN11 Figure 4-10. Port L I/O Register (PTL) MC9S12HZ256 Data Sheet, Rev. 2. PTL2 PTL1 PTL0 AN10 AN9 AN8 Freescale Semiconductor ...
Page 131
... Data Direction Register bit has no effect LCD frontplane driver is disabled (or LCD module is disabled), the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin. Field 7:0 Data Direction Port L DDRL[7:0] 0 Associated pin is configured as input. 1 Associated pin is configured as output. Freescale Semiconductor PTIL5 PTIL4 PTIL3 Figure 4-11 ...
Page 132
... Pull Device Enable Port L PERL[7:0] 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled. 132 RDRL5 RDRL4 RDRL3 Table 4-10. RDRL Field Descriptions Description PERL5 PERL4 PERL3 Table 4-11. PERL Field Descriptions Description MC9S12HZ256 Data Sheet, Rev. 2. RDRL2 RDRL1 RDRL0 PERL2 PERL1 PERL0 Freescale Semiconductor ...
Page 133
... The Port L Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1. Field 7:0 Pull Select Port L PPSL[7: pull-up device is connected to the associated port L pin pull-down device is connected to the associated port L pin. Freescale Semiconductor PPSL5 PPSL4 PPSL3 1 ...
Page 134
... This register always reads back the status of the associated pins. 134 5 4 PTM5 PTM4 PTM3 TXCAN1 RXCAN1 TXCAN0 0 0 Figure 4-16. Port M I/O Register (PTM PTIM5 PTIM4 PTIM3 Unaffected by reset Figure 4-17. Port M Input Register (PTIM) MC9S12HZ256 Data Sheet, Rev. 2. PTM2 RXCAN0 PTIM2 Freescale Semiconductor ...
Page 135
... This register configures the drive strength of configured output pins as either full or reduced pin is configured as input, the corresponding Reduced Drive Register bit has no effect. Field 5:2 Reduced Drive Port M RDRM[5:2] 0 Full drive strength at output 1 Associated pin drives at about 1/3 of the full drive strength. Freescale Semiconductor DDRM5 DDRM4 DDRM3 0 ...
Page 136
... If a CAN module is enabled, a pull-up device can be activated on the receiver pin, and on the transmitter pin if the corresponding wired-OR mode bit is set. Pull-down devices can not be activated on CAN pins. 136 PERM5 PERM4 PERM3 Table 4-15. PERM Field Descriptions Description PPSM5 PPSM4 PPSM3 MC9S12HZ256 Data Sheet, Rev. 2. PERM2 PPSM2 Freescale Semiconductor ...
Page 137
... These bits apply also to the CAN transmitter and allow a multipoint connection of several serial modules. Field 5:2 Wired-OR Mode Port M WOMM[5:2] 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. Freescale Semiconductor Table 4-16. PPSM Field Descriptions Description WOMM5 WOMM4 ...
Page 138
... I/O function, and the corresponding RXD1 pin is configured as an input. 138 PTP5 PTP4 PTP3 SCL SDA PWM5 PWM4 PWM3 Figure 4-23. Port P I/O Register (PTP) MC9S12HZ256 Data Sheet, Rev. 2. PTP2 PTP1 PTP0 RXD1 TXD1 PWM2 PWM1 PWM0 Freescale Semiconductor ...
Page 139
... If the PWM, IIC and SCI1 functions are disabled, the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin. Field 5:0 Data Direction Port P DDRP[5:0] 0 Associated pin is configured as input. 1 Associated pin is configured as output. Freescale Semiconductor PTIP5 PTIP4 PTIP3 u ...
Page 140
... Reduced Drive Register bit has no effect. Field 5:0 Reduced Drive Port P RDRP[5:0] 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength. 140 RDRP5 RDRP4 RDRP3 Table 4-19. RDRP Field Descriptions Description MC9S12HZ256 Data Sheet, Rev. 2. RDRP2 RDRP1 RDRP0 Freescale Semiconductor ...
Page 141
... The Port P Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1. Field 5:0 Polarity Select Port P PPSP[5: pull-up device is connected to the associated port P pin pull-down device is connected to the associated port P pin. Freescale Semiconductor PERP5 PERP4 PERP3 0 ...
Page 142
... Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. 0 Wired-OR Mode Port P WOMP0 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. 142 WOMP5 WOMP4 Table 4-22. WOMP Field Descriptions Description MC9S12HZ256 Data Sheet, Rev. 2. WOMP2 WOMPO Freescale Semiconductor ...
Page 143
... The SPI function takes precedence over the general-purpose I/O function if the SPI is enabled. If enabled, the SCI0 transmitter takes precedence over the general-purpose I/O function, and the corresponding TXD0 pin is configured as an output. If enabled, the SCI0 receiver takes precedence over the general-purpose I/O function, and the corresponding RXD0 pin is configured as an input. Freescale Semiconductor ...
Page 144
... Data Direction Port S DDRS[1:0] 0 Associated pin is configured as input. 1 Associated pin is configured as output. 144 PTIS5 PTIS4 Unaffected by reset Figure 4-31. Port S Input Register (PTIS DDRS5 DDRS4 Table 4-23. DDRS Field Descriptions Description MC9S12HZ256 Data Sheet, Rev. 2. PTIS1 PTIS0 DDRS1 DDRS0 Freescale Semiconductor ...
Page 145
... Reduced Drive Port S RDRS[7:4] 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength. 1:0 Reduced Drive Port S RDRS[1:0] 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength. Freescale Semiconductor RDRS5 RDRS4 Table 4-24. RDRS Field Descriptions Description MC9S12HZ256 Data Sheet, Rev ...
Page 146
... The Port S Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1. 146 PERS5 PERS4 Table 4-25. PERS Field Descriptions Description PPSS5 PPSS4 MC9S12HZ256 Data Sheet, Rev. 2. PERS1 PERS0 PPSS1 PPSS0 Freescale Semiconductor ...
Page 147
... Field 7:4 Wired-OR Mode Port S WOMS[7:4] 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. 1:0 Wired-OR Mode Port S WOMS[1:0] 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. Freescale Semiconductor Table 4-26. PPSS Field Descriptions Description WOMS5 WOMS4 Table 4-27 ...
Page 148
... If the associated data direction bit (DDRTx) is set to 0 (input) and the LCD frontplane driver is disabled (or LCD module is disabled), a read returns the value of the pin. 148 PTT5 PTT4 PTT3 OC5 OC4 OC3 Figure 4-37. Port T I/O Register (PTT) MC9S12HZ256 Data Sheet, Rev. 2. PTT2 PTT1 PTT0 OC2 OC1 OC0 Freescale Semiconductor ...
Page 149
... If the TIM module is enabled, each port pin configured as an input capture has the corresponding Data Direction Register bit controlling the I/O direction of the associated pin. Field 7:0 Data Direction Port T DDRT[7:0] 0 Associated pin is configured as input. 1 Associated pin is configured as output. Freescale Semiconductor PTIT5 PTIT4 PTIT3 u ...
Page 150
... Reduced Drive Register bit has no effect. Field 7:0 Reduced Drive Port T RDRT[7:0] 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength. 150 RDRT5 RDRT4 RDRT3 Table 4-29. RDRT Field Descriptions Description MC9S12HZ256 Data Sheet, Rev. 2. RDRT2 RDRT1 RDRT0 Freescale Semiconductor ...
Page 151
... The Port T Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1. Field 7:0 Pull Select Port T PPST[7: pull-up device is connected to the associated port T pin pull-down device is connected to the associated port T pin. Freescale Semiconductor PERT5 PERT4 PERT3 1 ...
Page 152
... If the associated data direction bit (DDRUx) is set to 0 (input) and the slew rate is disabled, a read returns the value of the pin. 152 PTU5 PTU4 PTU3 M1COP M1COM M0C1P M1COSP M1COSM M0SINP Figure 4-43. Port U I/O Register (PTU) MC9S12HZ256 Data Sheet, Rev. 2. PTU2 PTU1 PTU0 M0C1M M0C0P M0C0M M0SINM M1COSP M0COSM Freescale Semiconductor ...
Page 153
... Data Direction Register bit has no effect. If the SSD and MC modules are disabled, the corresponding Data Direction Register bits revert to control the I/O direction of the associated pins. Field 7:0 Data Direction Port U DDRU[7:0] 0 Associated pin is configured as input. 1 Associated pin is configured as output. Freescale Semiconductor PTIU5 PTIU4 PTIU3 u ...
Page 154
... Pull Device Enable Port U PERU[7:0] 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled. 154 SRRU5 SRRU4 SRRU3 Table 4-33. SRRU Field Descriptions Description PERU5 PERU4 PERU3 Table 4-34. PERU Field Descriptions Description MC9S12HZ256 Data Sheet, Rev. 2. SRRU2 SRRU1 SRRU0 PERU2 PERU1 PERU0 Freescale Semiconductor ...
Page 155
... The Port U Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1. Field 7:0 Pull Select Port U PPSU[7: pull-up device is connected to the associated port U pin pull-down device is connected to the associated port U pin. Freescale Semiconductor PPSU5 PPSU4 PPSU3 0 ...
Page 156
... If the associated data direction bit (DDRVx) is set to 0 (input) and the slew rate is disabled, a read returns the value of the pin. 156 PTV5 PTV4 PTV3 M3C0P M3C0M M2C1P M3COSP M3COSM M2SINP Figure 4-49. Port V I/O Register (PTV) MC9S12HZ256 Data Sheet, Rev. 2. PTV2 PTV1 PTV0 M2C1M M2C0P M2C0M M2SINM M2COSP M2COSM Freescale Semiconductor ...
Page 157
... Data Direction Register bit has no effect. If the SSD and MC modules are disabled, the corresponding Data Direction Register bits revert to control the I/O direction of the associated pins. Field 7:0 Data Direction Port V DDRV[7:0] 0 Associated pin is configured as input. 1 Associated pin is configured as output. Freescale Semiconductor PTIV5 PTIV4 PTIV3 u ...
Page 158
... Pull Device Enable Port V PERV[7:0] 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled. 158 SRRV5 SRRV4 SRRV3 Table 4-37. SRRV Field Descriptions Description PERV5 PERV4 PERV3 Table 4-38. PERV Field Descriptions Description MC9S12HZ256 Data Sheet, Rev. 2. SRRV2 SRRV1 SRRV0 PERV2 PERV1 PERV0 Freescale Semiconductor ...
Page 159
... The Port V Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1. Field 7:0 Pull Select Port V PPSV[7: pull-up device is connected to the associated port V pin pull-down device is connected to the associated port V pin. Freescale Semiconductor PPSV5 PPSV4 PPSV3 0 ...
Page 160
... Register bit set to 0 configures the pin as an input. A Data Direction Register bit set to 0 configures the pin as an output peripheral module controls the pin the contents of the data direction register is ignored (Figure 4-55). 160 MC9S12HZ256 Data Sheet, Rev. 2.05 (Figure 4-55). (Figure 4-55). It can Freescale Semiconductor ...
Page 161
... If the port is used as an output the Reduced Drive Register allows the configuration of the drive strength. 4.4.5 Pull Device Enable Register The Pull Device Enable Register turns on a pull-up or pull-down device. The pull device becomes active only if the pin is used as an input wired-or output. Freescale Semiconductor PTIx 0 1 PTx ...
Page 162
... Disabled Pull Up Disabled Pull Down Disabled Disabled Falling Edge Disabled Rising Edge Pull Up Falling Edge Pull Down Rising Edge Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Falling Edge Disabled Rising Edge Disabled Falling Edge Disabled Rising Edge Freescale Semiconductor ...
Page 163
... Input L Input U Input V Input AD Input 1 PE[1:0] pins have pull-ups instead of pull-downs. Freescale Semiconductor Table 4-41. Port Reset State Summary Reset States Red. Drive/ Pull Mode Slew Rate Pull Down Refer to section Bus Control and Input/Output Pull Down 1 Pull Down Pull Down ...
Page 164
... Table 4-42. Pulse Detection Criteria Mode STOP Unit t <= 3 Bus Clock pulse 3 < t < 4 Bus Clock 3.2 < t pulse t >= 4 Bus Clock pulse MC9S12HZ256 Data Sheet, Rev. 2.05 (Figure 4-57 1 STOP Unit t <= 3.2 s pulse < pulse t > pulse Freescale Semiconductor and ...
Page 165
... Operation in Stop Mode All clocks are stopped in STOP mode. The port integration module has asynchronous paths on port AD to generate wake-up interrupts from stop mode. For other sources of external interrupts refer to the respective block description chapters. Freescale Semiconductor Chapter 4 Port Integration Module (PIM9HZ256V2) t pulse Figure 4-58 ...
Page 166
... Chapter 4 Port Integration Module (PIM9HZ256V2) 166 MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor ...
Page 167
... System reset generation from the following possible sources: — Power-on reset — Low voltage reset Refer to the device overview section for availability of this feature. — COP reset — Loss of clock reset — External pin reset • Real-time interrupt (RTI) Freescale Semiconductor MC9S12HZ256 Data Sheet, Rev. 2.05 167 ...
Page 168
... Self-clock mode should be used for safety purposes only. It provides reduced functionality to the MCU in case a loss of clock is causing severe system conditions. 5.1.3 Block Diagram Figure 5-1 shows a block diagram of the CRG. 168 MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor ...
Page 169
... PLL. Refer to the device overview chapter for calculation of PLL loop filter (XFC) components. If PLL usage is not required the XFC pin must be tied DDPLL Freescale Semiconductor Power-on Reset 1 Low Voltage Reset CRG Reset ...
Page 170
... CTCTL is intended for factory test purposes only. 170 CS MCU RS XFC Figure 5-2. PLL Loop Filter Connections Table 5-1. CRG Memory Map Use MC9S12HZ256 Data Sheet, Rev. 2.05 V DDPLL CP Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Freescale Semiconductor ...
Page 171
... REFDV CTFLG CRGFLG R RTIF W CRGINT R RTIE W CLKSEL R PLLSEL W PLLCTL R CME W RTICTL COPCTL R WCOP W FORBYP CTCTL Freescale Semiconductor NOTE SYN5 SYN4 REFDV3 PORF LVRF LOCKIF 0 0 LOCKIE PSTP SYSWAI ROAWAI PLLON AUTO ACQ RTR6 RTR5 RTR4 0 0 RSBCK Unimplemented or Reserved Figure 5-3. CRG Register Summary MC9S12HZ256 Data Sheet, Rev ...
Page 172
... Write to this register initializes the lock detector bit and the track detector bit. 172 Bit 6 Bit 5 Bit 4 = Unimplemented or Reserved SYNR = PLLCLK 2xOSCCLKx ---------------------------------- - REFDV NOTE SYN5 SYNR SYN3 NOTE MC9S12HZ256 Data Sheet, Rev. 2. Bit Bit 3 Bit 2 Bit 1 Bit 0 ). SCM SYN2 SYN1 0 0 Freescale Semiconductor 0 0 SYN0 0 ...
Page 173
... W Reset Unimplemented or Reserved Figure 5-6. CRG Reserved Register (CTFLG) Read: always reads 0x0000 in normal modes Write: unimplemented in normal modes Writing to this register when in special mode can alter the CRG functionality. Freescale Semiconductor Chapter 5 Clocks and Reset Generator (CRGV4 REFDV3 NOTE ...
Page 174
... Track Status Bit — TRACK reflects the current state of PLL track condition. This bit is cleared in self-clock mode. TRACK Writes have no effect. 0 Acquisition mode status. 1 Tracking mode status. 174 LOCK LVRF LOCKIF Note Figure 5-7. CRG Flag Register (CRGFLG) Table 5-2. CRGFLG Field Descriptions Description MC9S12HZ256 Data Sheet, Rev. 2. TRACK SCM SCMIF Freescale Semiconductor ...
Page 175
... Interrupt will be requested whenever RTIF is set. 4 Lock Interrupt Enable Bit LOCKIE 0 LOCK interrupt requests are disabled. 1 Interrupt will be requested whenever LOCKIF is set. 1 Self-Clock Mode Interrupt Enable Bit SCMIE 0 SCM interrupt requests are disabled. 1 Interrupt will be requested whenever SCMIF is set. Freescale Semiconductor Description . SCM LOCKIE 0 ...
Page 176
... Core Stops in Wait Mode Bit — Write: anytime CWAI 0 Core clock keeps running in wait mode. 1 Core clock stops in wait mode. 176 Figure 5- SYSWAI ROAWAI PLLWAI Table 5-4. CLKSEL Field Descriptions Description MC9S12HZ256 Data Sheet, Rev. 2.05 for details on the effect of each bit CWAI RTIWAI COPWAI 0 0 Freescale Semiconductor 0 0 ...
Page 177
... Automatic mode control is disabled and the PLL is under software control, using ACQ bit. 1 Automatic mode control is enabled and ACQ bit has no effect. 4 Acquisition Bit — Write anytime. If AUTO=1 this bit has no effect. ACQ 0 Low bandwidth filter is selected. 1 High bandwidth filter is selected. Freescale Semiconductor Description AUTO ...
Page 178
... Table 5-6. RTICTL Field Descriptions Description Table 5-7 shows all possible divide values selectable by the RTICTL register. The MC9S12HZ256 Data Sheet, Rev. 2.05 Section 5.5.1, “Clock Monitor Reset”). Section 5.4.7.2, “Self-Clock Mode”). RTR2 RTR1 RTR0 Table Freescale Semiconductor 5-7. ...
Page 179
... OFF* 1010 ( 11) OFF* 1011 ( 12) OFF* 1100 ( 13) OFF* 1101 ( 14) OFF* 1110 ( 15) OFF* 1111 ( 16) * Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility. Freescale Semiconductor Table 5-7. RTI Frequency Divide Rates RTR[6:4] = 001 010 011 ...
Page 180
... ARMCOP register) 180 Table 5-8. COPCTL Field Descriptions Description Table 5-9. COP Watchdog Rates OSCCLK CR1 CR0 Cycles to Time Out 0 0 COP disabled MC9S12HZ256 Data Sheet, Rev. 2. CR2 CR1 0 0 Table 5-9 Table 5-9). The COP Freescale Semiconductor 0 CR0 0 shows ...
Page 181
... Writing to this register when in special test modes can alter the CRG’s functionality Reset Unimplemented or Reserved Read: always read 0x0080 except in special modes Write: only in special modes Freescale Semiconductor NOTE Figure 5-13. Reserved Register (FORBYP) NOTE 5 ...
Page 182
... The PLL can change between acquisition and tracking modes either automatically or manually. 182 Bit 5 Bit 4 Bit Figure 5-15. ARMCOP Register Diagram SYNR PLLCLK 2 OSCCLK = ---------------------------------- - REFDV CAUTION MC9S12HZ256 Data Sheet, Rev. 2. Bit 2 Bit 1 Bit Freescale Semiconductor ...
Page 183
... The lock detector compares the frequencies of the feedback clock, and the reference clock. Therefore, the speed of the lock detector is directly proportional to the final reference frequency. The circuit determines the mode of the PLL and the lock condition based on this comparison. Freescale Semiconductor REFERENCE REFDV <3:0> ...
Page 184
... The following conditions apply when in sys MC9S12HZ256 Data Sheet, Rev. 2.05 , and is clear when trk , and is cleared Lock . ) before acq ) before selecting the PLLCLK al Freescale Semiconductor ...
Page 185
... PLL clock mode is selected with PLLSEL bit in the CLKSEL register. When selected, the PLL output clock drives SYSCLK for the main system including the CPU and peripherals. The PLL cannot be turned off by clearing the PLLON bit, if the PLL clock is selected. When PLLSEL is changed, it takes a maximum Freescale Semiconductor PLLSEL or SCM 1 ...
Page 186
... A number greater equal than 4096 rising OSCCLK edges within a check window is called osc ok. Note that osc ok immediately terminates the current check window. See 1. VCO clock cycles are generated by the PLL when running at minimum frequency f 186 1 is called check window. Figure 5-19 MC9S12HZ256 Data Sheet, Rev. 2. example. . SCM Freescale Semiconductor ...
Page 187
... Figure 5-20. Sequence for Clock Quality Check Remember that in parallel to additional actions caused by self-clock mode or clock monitor reset check the OSCCLK signal Clock Monitor Reset will always set the SCME bit to logical’1’ Freescale Semiconductor check window 4096 4095 osc ok Figure 5-19 ...
Page 188
... Reset).” The COP runs with a gated OSCCLK (see COP”). Three control bits in the COPCTL register allow selection MC9S12HZ256 Data Sheet, Rev. 2.05 ) and an active VREG CR[2:0] 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 COP TIMEOUT Section 5.5.2, Freescale Semiconductor ...
Page 189
... Self-Clock Mode The VCO has a minimum operating frequency failure or due to long crystal start-up time, the bus clock and the core clock are derived from the VCO Freescale Semiconductor RTI”). At the end of the RTI time-out period the . WAIT(RTIWAI), RTI enable ...
Page 190
... MC9S12HZ256 Data Sheet, Rev. 2.05 Section 5.4.4, “Clock Quality COPWAI ROAWAI — — — — — — — — stopped — 1 — reduced Figure 5-23). Depending on Freescale Semiconductor ...
Page 191
... Core req’s Wait Mode. no PLLWAI=1 ? yes CWAI or Clear SYSWAI=1 PLLSEL, ? Disable PLL yes Disable core clocks Figure 5-23. Wait Mode Entry/Exit Sequence Freescale Semiconductor no no SYSWAI=1 ? yes Disable Enter system clocks Wait Mode Wait Mode left due to external reset Exit Wait w. ext.RESET no Exit Wait w ...
Page 192
... If wait mode is entered from self-clock mode, the CRG will continue to check the clock quality until clock check is successful. The PLL and voltage regulator (VREG) will remain enabled. Table 5-11 summarizes the outcome of a clock loss while in wait mode. 192 MC9S12HZ256 Data Sheet, Rev. 2.05 Section 5.4.4, “Clock Freescale Semiconductor ...
Page 193
... Continue to perform additional Clock Quality Checks until OSCCLK or an External RESET is applied. – Exit Wait Mode in SCM using PLL clock (f – Start reset sequence, – Continue to perform additional Clock Quality Checks until OSCCLK Freescale Semiconductor CRG Actions while in Wait Mode. is o.k. again. is o.k.again. ...
Page 194
... A complete timeout window check will be started when stop mode is exited again. Wake-up from stop mode also depends on the setting of the PSTP bit. 194 CRG Actions ) as system clock, SCM MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor ...
Page 195
... Wake-up from pseudo-stop is the same as wake-up from wait mode. There are also three different scenarios for the CRG to restart the MCU from pseudo-stop mode: • External reset • Clock monitor fail • Wake-up interrupt Freescale Semiconductor Core req’s Stop Mode. Clear PLLSEL, Disable PLL Wait Mode left Enter ...
Page 196
... MCU runs on OSCCLK after leaving stop mode. The software must set the PLLSEL bit again, in order to switch system and core clocks to the PLLCLK. Table 5-12 summarizes the outcome of a clock loss while in pseudo-stop mode. 196 MC9S12HZ256 Data Sheet, Rev. 2.05 Section 5.4.4, “Clock Freescale Semiconductor ...
Page 197
... External RESET is applied. – Exit Pseudo-Stop Mode in SCM using PLL clock (f – Start reset sequence, – Continue to perform additional Clock Quality Checks until OSCCLK is o.k.again. Freescale Semiconductor Chapter 5 Clocks and Reset Generator (CRGV4) CRG Actions MC9S12HZ256 Data Sheet, Rev. 2. system clock ...
Page 198
... The reset values of registers and signals are provided in 198 CRG Actions Checker”). After completing the clock quality check Checker”). If the clock quality check is successful, the NOTE Section 5.3, “Memory Map and Register MC9S12HZ256 Data Sheet, Rev. 2. system clock, SCM Freescale Semiconductor ...
Page 199
... External circuitry connected to the RESET pin should not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic 1 within 64 SYSCLK cycles after the low drive is released. Freescale Semiconductor Table 5-13. Refer to the device overview chapter for related Table 5-13 ...
Page 200
... CRG drives RESET pin low RESET pin released ) ( 128+n cycles 64 cycles with n being possibly min 3 / max 6 SYSCLK cycles depending not on internal running synchronization delay Figure 5-25. RESET Timing MC9S12HZ256 Data Sheet, Rev. 2. possibly RESET driven low externally Section 5.3, Freescale Semiconductor ...