MC9S12HZ128CAL Freescale Semiconductor, MC9S12HZ128CAL Datasheet - Page 213

• Manufacturer Part Number: MC9S12HZ128CAL
• Description: IC MCU 16BIT 128K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128CAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.3.2.2
Writes to this register will abort current conversion sequence but will not start a new sequence.
Read: Anytime
Write: Anytime
Freescale Semiconductor
ETRIGCH[3:0]
ETRIGSEL
Reset
Field
3:0
W
7
R
ETRIGSEL
ATD Control Register 1 (ATDCTL1)
0
7
External Trigger Source Select — This bit selects the external trigger source to be either one of the AD
channels or one of the ETRIG[3:0] inputs. See device specification for availability and connectivity of
ETRIG[3:0] inputs. If ETRIG[3:0] input option is not available, writing a 1 to ETRISEL only sets the bit but has
no effect, that means one of the AD channels (selected by ETRIGCH[3:0]) remains the source for external
trigger. The coding is summarized in
External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG[3:0] inputs
as source for the external trigger. The coding is summarized in
WRAP3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
= Unimplemented or Reserved
0
0
6
WRAP2
Table 7-3. Multi-Channel Wrap Around Coding
Figure 7-4. ATD Control Register 1 (ATDCTL1)
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Table 7-4. ATDCTL1 Field Descriptions
MC9S12HZ256 Data Sheet, Rev. 2.05
0
0
5
WRAP1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Table
WRAP0
7-5.
0
0
4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
ETRIGCH3
(MULT = 1) Wrap Around to AN0
Multiple Channel Conversions
Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)
1
3
after Converting
Table
Reserved
ETRIGCH2
AN10
AN11
AN12
AN13
AN14
AN15
7-5.
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
1
2
ETRIGCH1
1
1
ETRIGCH0
1
0
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