MC9S12HZ128CAL Freescale Semiconductor, MC9S12HZ128CAL Datasheet - Page 503

• Manufacturer Part Number: MC9S12HZ128CAL
• Description: IC MCU 16BIT 128K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128CAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.2
Due to the nature of VREG3V3 being a voltage regulator providing the chip internal power supply
voltages most signals are power supply signals connected to pads.
Table 17-1
17.2.1
Signal V
this pin. A chip external decoupling capacitor (100 nF...220 nF, X7R ceramic) between V
can smoothen ripple on V
For entering Shutdown Mode, pin V
17.2.2
Signals V
regulator. Internal precision reference circuits are supplied from these signals. A chip external decoupling
capacitor (100 nF...220 nF, X7R ceramic) between V
supply.
Freescale Semiconductor
V
REGEN
V
V
Name
DDR
V
V
V
DDPLL
V
SSPLL
External Signal Description
V
DDA
DDR
DDA
SSA
DD
SS
(optional)
shows all signals of VREG3V3 associated with pins.
V
V
is the power input of VREG3V3. All currents sourced into the regulator loads flow through
DDR
DDA
/V
Check device overview chapter for connectivity of the signals.
SSA
, V
— Regulator Power Input
which are supposed to be relatively quiet are used to supply the analog parts of the
SSA
Port
DDR
—
—
—
—
—
—
—
—
— Regulator Reference Supply
.
Table 17-1. VREG3V3 — Signal Properties
VREG3V3 power input (positive supply)
VREG3V3 quiet input (positive supply)
VREG3V3 quiet input (ground)
VREG3V3 primary output (positive supply)
VREG3V3 primary output (ground)
VREG3V3 secondary output (positive supply)
VREG3V3 secondary output (ground)
VREG3V3 (Optional) Regulator Enable
DDR
MC9S12HZ256 Data Sheet, Rev. 2.05
should also be tied to ground on devices without a V
NOTE
Function
DDA
and V
Chapter 17 Dual Output Voltage Regulator (VREG3V3V2)
SSA
can further improve the quality of this
Reset State
—
—
—
—
—
—
—
—
DDR
REGEN
and V
Pull Up
—
—
—
—
—
—
—
—
SSR
pin.
503