MC68332GVEH25 Freescale Semiconductor, MC68332GVEH25 Datasheet - Page 198

• Manufacturer Part Number: MC68332GVEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332GVEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 132-QFP
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Data Ram Size: 2 KB
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

A-24
Num
Num
E10
E11
E12
E13
E14
E15
E10
E11
E12
E13
E14
E15
E1
E2
E3
E4
E5
E6
E7
E8
E9
E1
E2
E3
E4
E5
E6
E7
E8
E9
Notes for Tables A–8 and A–8a:
1. All AC timing is shown with respect to 20% V
2. When the previous bus cycle is not an ECLK cycle, the address may be valid before ECLK goes low.
3. Address access time = t
4. Chip select access time = t
ECLK Low to Address Valid
ECLK Low to Address Hold
ECLK Low to CS Valid (CS delay)
ECLK Low to CS Hold
CS Negated Width
Read Data Setup Time
Read Data Hold Time
ECLK Low to Data High Impedance
CS Negated to Data Hold (Read)
CS Negated to Data High Impedance
ECLK Low to Data Valid (Write)
ECLK Low to Data Hold (Write)
Address Access Time (Read)
Chip Select Access Time (Read)
Address Setup Time
ECLK Low to Address Valid
ECLK Low to Address Hold
ECLK Low to CS Valid (CS delay)
ECLK Low to CS Hold
CS Negated Width
Read Data Setup Time
Read Data Hold Time
ECLK Low to Data High Impedance
CS Negated to Data Hold (Read)
CS Negated to Data High Impedance
ECLK Low to Data Valid (Write)
ECLK Low to Data Hold (Write)
Address Access Time (Read)
Chip Select Access Time (Read)
Address Setup Time
Table A-8a 20.97 MHz ECLK Bus Timing
Freescale Semiconductor, Inc.
Table A-8 16.78 MHz ECLK Bus Timing
Ecyc
(V
For More Information On This Product,
(V
Ecyc
Characteristic
Characteristic
DD
– t
DD
2
2
EAD
– t
ELECTRICAL CHARACTERISTICS
= 5.0 Vdc
= 5.0 Vdc
3
3
ECSD
– t
4
4
Go to: www.freescale.com
EDSR
– t
EDSR
.
10%, V
5%, V
DD
.
and 70% V
SS
SS
= 0 Vdc, T
= 0 Vdc, T
DD
levels unless otherwise noted.
A
A
= T
= T
L
L
to T
Symbol
Symbol
to T
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
EDDW
EDHW
EDDW
EDHW
t
ECSD
ECSH
ECSN
EDSR
EDHR
ECDH
EACC
t
ECSD
ECSH
ECSN
EDSR
EDHR
ECDH
EACC
t
EDHZ
ECDZ
EACS
t
t
EDHZ
ECDZ
EACS
t
EAD
EAH
EAS
EAD
EAH
EAS
H
H
)
)
Min
386
296
Min
308
236
1/2
1/2
15
15
30
30
15
10
10
25
25
10
—
—
—
—
—
—
—
—
—
—
5
0
5
0
USER’S MANUAL
Max
Max
150
120
60
60
48
48
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
2
1
2
MC68332
Unit
Unit
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
cyc
cyc
cyc
cyc