MC68332GVEH25 Freescale Semiconductor, MC68332GVEH25 Datasheet - Page 81

• Manufacturer Part Number: MC68332GVEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332GVEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 132-QFP
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Data Ram Size: 2 KB
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.6.3.2 Clock Mode Selection
4.6.3.3 Breakpoint Mode Selection
4.6.4 MCU Module Pin Function During Reset
MC68332
USER’S MANUAL
The state of the clock mode (MODCLK) pin during reset determines what clock source
the MCU uses. When MODCLK is held high during reset, the clock signal is generated
from a reference frequency. When MODCLK is held low during reset, the clock syn-
thesizer is disabled, and an external system clock signal must be applied. Refer to 4.3
System Clock for more information.
The MCU uses internal and external breakpoint (BKPT) signals. During reset excep-
tion processing, at the release of the RESET signal, the CPU32 samples these signals
to determine how to handle breakpoints.
If either BKPT signal is at logic level zero when sampled, an internal BDM flag is set,
and the CPU32 enters background debugging mode whenever either BKPT input is
subsequently asserted.
If both BKPT inputs are at logic level one when sampled, breakpoint exception pro-
cessing begins whenever either BKPT signal is subsequently asserted.
Refer to SECTION 5 CENTRAL PROCESSING UNIT for more information on back-
ground debugging mode and exceptions. Refer to 4.5.4 CPU Space Cycles for infor-
mation concerning breakpoint acknowledge bus cycles.
Usually, module pins default to port functions, and input/output ports are set to input
state. This is accomplished by disabling pin functions in the appropriate control regis-
ters, and by clearing the appropriate port data direction registers. Refer to individual
module sections in this manual for more information. Table 4-17 is a summary of mod-
ule pin function out of reset. Refer to APPENDIX D REGISTER SUMMARY for register
function and reset state.
The MODCLK pin can also be used as parallel I/O pin PF0. To pre-
vent inadvertent clock mode selection by logic connected to port F,
use an active device to drive MODCLK during reset.
Freescale Semiconductor, Inc.
For More Information On This Product,
SYSTEM INTEGRATION MODULE
Go to: www.freescale.com
NOTE
4-41