MCIMX512DJM8C Freescale Semiconductor, MCIMX512DJM8C Datasheet - Page 104

MULTIMEDIA PROC 529-LFBGA

MCIMX512DJM8C

Manufacturer Part Number
MCIMX512DJM8C
Description
MULTIMEDIA PROC 529-LFBGA
Manufacturer
Freescale Semiconductor
Series
i.MX51r
Datasheets

Specifications of MCIMX512DJM8C

Core Processor
ARM Cortex-A8
Core Size
32-Bit
Speed
800MHz
Connectivity
1-Wire, EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
128
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.8 V ~ 1.15 V
Oscillator Type
External
Operating Temperature
-20°C ~ 85°C
Package / Case
529-LFBGA
Processor Series
i.MX51
Core
ARM Cortex A8
Data Bus Width
32 bit
Program Memory Size
36 KB
Data Ram Size
128 KB
Interface Type
I2C, SPI, SSI, UART, USB
Maximum Clock Frequency
200 MHz
Number Of Timers
5
Operating Supply Voltage
0.8 V to 1.15 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
MCIMX51EVKJ
Minimum Operating Temperature
- 20 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

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Manufacturer
Quantity
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Part Number:
MCIMX512DJM8C
Manufacturer:
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Quantity:
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Part Number:
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Manufacturer:
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Quantity:
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1
Electrical Characteristics
104
IP32
IP33
IP34
IP35
IP36
IP37
IP38
IP47
This parameter is a requirement to the display connected to the IPU.
IP27 Read system cycle time
IP28 Write system cycle time
IP29 RS start
IP30 CS start
IP31 CS hold
IP32 RS hold
IP33 Controls setup time for read Tdcsr
IP34 Controls hold time for read
IP35 Controls setup time for write Tdcsw
IP36 Controls hold time for write
IP37 Slave device data delay
IP38 Slave device data hold time
ID
ID
RS hold
Read start
Read hold
Write start
Controls hold time for write
Slave device data delay
Slave device data hold time
Read time point
Table 83. Asynchronous Display Interface Timing Parameters (Pixel Level) (continued)
Parameter
Table 84. Asynchronous Parallel Interface Timing Parameters (Access Level)
Parameter
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
13
12
1
8
3
Tcycr
Tcycw
Tdcsrr
Tdcsc
Tdchc
Tdchrr
Tdchr
Tdchw
Tracc
Troh
Symbol
Tdchrr
Tdcsr
Tdchr
Tdcsw
Tdchw
Tracc
Troh
Tdrp
Symbol
Tdicpr–1.5
Tdicpw–1.5
Tdicurs–1.5
Tdicucs–1.5
TdicdcsTdicucs–1.5
Tdicdrs–Tdicurs–1.5
Tdicur–1.5
Tdicdr–Tdicur–1.5
Tdicuw–1.5
Tdicdw–Tdicuw–1.5
Tdrp–Tlbd–Tdicdr+1.5
Hold time of data on the buss Time that display read data is valid
Min
Delay of incoming data
0
Data sampling point
DOWN#
DOWN#
DOWN#
Value
UP#
UP#
Tdicpr
Tdicpw
Tdicurs
Tdicur
Tdicdcs
Tdicdrs
Tdicur
Tdicdr
Tdicuw
Tdicpw
2
8
3
10
–Tdicur
Typ
6
4
–Tdicurs
–Tdicucs
–Tdicuw
1
RS strobe release, predefined
value in DI REGISTER
read strobe switch, predefined
value in DI REGISTER
read strobe release signal,
predefined value in DI REGISTER
write strobe switch, predefined
value in DI REGISTER
write strobe release, predefined
value in DI REGISTER
Physical delay of display’s data,
defined from Read access local
start point
in input bus
Point of input data sampling by DI,
predefined in DC Microcode
9
7
11
5
Tdicpr+1.5
Tdicpw+1.5
Tdicurs+1.5
Tdicucs+1.5
Tdicdcs–Tdicucs+1.5
Tdicdrs–Tdicurs+1.5
Tdicur+1.5
Tdicdr–Tdicur+1.5
Tdicuw+1.5
Tdicdw–Tdicuw+1.5
Tdrp
Tdicpr–Tdicdr–1.5
Description
13
–Tlbd
Freescale Semiconductor
Max
14
–Tdicur–1.5
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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