MCIMX512DJM8C Freescale Semiconductor, MCIMX512DJM8C Datasheet - Page 69

• Manufacturer Part Number: MCIMX512DJM8C
• Description: MULTIMEDIA PROC 529-LFBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX51r

Specifications of MCIMX512DJM8C

• Core Processor: ARM Cortex-A8
• Core Size: 32-Bit
• Speed: 800MHz
• Connectivity: 1-Wire, EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 128
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.8 V ~ 1.15 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 529-LFBGA
• Processor Series: i.MX51
• Core: ARM Cortex A8
• Data Bus Width: 32 bit
• Program Memory Size: 36 KB
• Data Ram Size: 128 KB
• Interface Type: I2C, SPI, SSI, UART, USB
• Maximum Clock Frequency: 200 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 0.8 V to 1.15 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: MCIMX51EVKJ
• Minimum Operating Temperature: - 20 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1. Test conditions are: Capacitance 15 pF for DDR PADS. Recommended drive strengths is medium for SDCLK and high for
2. SDRAM CLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal
3. Test conditions are: Capacitance 15 pF for DDR PADS. Recommended drive strengths is medium for SDCLK and high for
4. SDRAM CLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal
Freescale Semiconductor
address and controls.
value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK
and SDCLK (inverted clock).
address and controls.
value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK
and SDCLK (inverted clock).
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
Table 62. Derating values for DDR2 Single Ended DQS
Table 61. Derating values for DDR2 Differential DQS
1
,
3
2
,
4
Electrical Characteristics
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