ATA6603P-PLQW Atmel, ATA6603P-PLQW Datasheet
ATA6603P-PLQW
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ATA6603P-PLQW Summary of contents
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... ATA6602/ATA6603 is a single-package dual-chip circuit family for LIN-bus slave node applications. It supports highly integrated solutions for in-vehicle LIN networks. The LIN-system-basis-chip (LIN-SBC) consists of a LIN transceiver, voltage regulator and window watchdog. The second chip is a microcontroller out of Atmel 8-bit microcontrollers with advanced RISC architecture. Figure 1-1. ...
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Pin Configuration Figure 2-1. Pinning QFN48 Table 2-1. Pin Description Pin Symbol Function 1 PC2 Port C 2 I/O line (ADC2/PCINT10) 2 PC3 Port C 3 I/O line (ADC3/PCINT11) 3 PC4 Port C 4 I/O line (ADC4/SDA/PCINT12) ...
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Table 2-1. Pin Description (Continued) Pin Symbol Function 19 RXD LIN bus receiver output 20 TXD LIN bus transmitter input 21 NRES Watchdog and undervoltage reset output 22 WD_OSC Watchdog oscillator timing-resistor connection 23 TM Tie to ground – for ...
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LIN System-basis-chip Block 3.1 Features • Supply Voltage up to 40V • Operating Voltage V • Slew Rate Control According to LIN Specification 2.0 • Supply Current During Sleep Mode Typically 10 µA • Supply Current in Silent Mode ...
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Figure 3-1. Block Diagram V DD Receiver RXD V S WAKE V DD TXD Time-out TXD Timer Debounce EN Time V GND DD TEMP GND 4921E–AUTO–09/09 Wake-up Bus Timer Slew Rate Control Control Unit Standby Mode Internal Testing Watchdog Unit ...
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Functional Description 3.3.1 Supply Pin (VS) The LIN operating voltage is V Pre-normal mode and the voltage regulator is switched on (that is, 5V/50 mA output capability). The supply current in Sleep mode is typically 10 µA, and 40 ...
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... For normal watchdog operation connect pin MODE via an external resistor to GND. For debug- ging your software you can connect pin MODE to 5V and the watchdog is switched off. 3.3.13 TM Input Pin Pin TM is used in final production measurement at Atmel. In the application it is always con- nected to GND. 4921E–AUTO–09/09 regulator is also 50 mA, but the V ...
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Modes of Operation Figure 3-2. Modes of Operation Normal Mode VCC: 5V 2%/50 mA with undervoltage monitoring Communication: ON 3.3.14.1 Normal Mode This is the normal transmitting and receiving mode. The voltage regulator is ...
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In Silent mode, the 5V regulator is in low tolerance mode (4.65V to 5.35V) and can source mA. The internal slave termination between pin LIN and pin VS is disabled to minimize the power dissipation in case ...
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Figure 3-4. LIN Bus TXD RXD VCC NRES 3.3.14.3 Sleep Mode The falling edge at EN has to occure not more than t ing edge at TXD in order to switch the IC into Sleep mode. The TXD Signal has ...
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With EN high you can switch directly from Silent mode to Normal mode. In the application where the LIN-SBC supplies the microcontroller, wake-up from Sleep mode is only possible via LIN or pin WAKE. If the device is switched into ...
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Figure 3-6. LIN bus RXD VCC Voltage Regulator NRES 3.3.14.4 Pre-normal Mode At system power-up the device automatically switches to Pre-normal mode. The voltage regula- tor is switched low for t off and the watchdog is active. ...
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Table 3-1. Mode of Operation Pre-normal Normal Silent Sleep 3.3.15 Wake-up Scenarios from Silent to Sleep Mode 3.3.15.1 Remote Wake-up via Dominant Bus State A falling edge at pin LIN followed by a dominant bus level maintained for a certain ...
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Figure 3-7. LIN Bus TXD RXD VCC NRES 3.3.16 Fail-safe Features • During a short circuit at LIN, the output limits the output current to I dissipation, the chip temperature exceeds T cools down and after a hysteresis of T ...
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If the WD_OSC pin has a short circuit to GND or the resistor is disconnected, the watchdog oscillator runs with a high frequency and guarantees a reset. In order to activate this feature in any condition it is recommended ...
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Figure 3-9. For programming purposes at the microcontroller it is potentially necessary to supply the VCC output via an external supply while the VS pin of the system basis chip is disconnected. This behavior is no problem for the system ...
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After ramping up the battery voltage V switched on. The reset output NRES stays low for the time t switches to high and the watchdog waits for the watchdog sequence from the microcontroller. This lead time t RXD switches to ...
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A microcontroller with an oscillator tolerance of ±15% is sufficient to supply the trigger inputs correctly within the time period of T Table 3-2. Rwd_osc 120 3.3.19 Temperature Monitor at Pin TEMP In addition to the ...
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Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated ...
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Electrical Characteristics 5V < V < 18V –40°C to +125°C S case No. Parameters Test Conditions 1 VS Pin Nominal DC voltage 1.1 range Sleep mode Supply current in Sleep 1.2 V lin mode V Bat Bus ...
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Electrical Characteristics (Continued) 5V < V < 18V –40°C to +125°C S case No. Parameters Test Conditions 5 NRES Output Pin V S 5.1 High-level output voltage I nres V S 5.2 Low-level output voltage I nres ...
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Electrical Characteristics (Continued) 5V < V < 18V –40°C to +125°C S case No. Parameters Test Conditions LIN Bus Driver: Bus Load Conditions: 8 Load1 (Small Load2 (Large): 10 nF, 500 ; ...
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Electrical Characteristics (Continued) 5V < V < 18V –40°C to +125°C S case No. Parameters Test Conditions 10 Internal Timers Dominant time for 10.1 V LIN wake-up via LIN bus Time delay for mode change from Pre-normal ...
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Electrical Characteristics (Continued) 5V < V < 18V –40°C to +125°C S case No. Parameters Test Conditions 13 Watchdog Oscillator Voltage at WD_OSC in 13.1 I WD_OSC Normal mode Possible values of 13.2 resistor 13.3 Oscillator period ...
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Figure 3-12. Definition of Bus Timing Parameters TXD (input to transmitting node) TH Rec(max Dom(max) (Transceiver supply of transmitting node) TH Rec(min) TH Dom(min) RXD (output of receiving node1) t rx_pdf(1) RXD (output of receiving node2) 4921E–AUTO–09/09 t ...
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Microcontroller Block 4.1 Features • High Performance, Low Power AVR 8-bit Microcontroller • Advanced RISC Architecture – 131 Powerful Instructions - Most Single Clock Cycle Execution – 32 – Fully Static Operation – MIPS Throughput at ...
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Overview The ATA6602/ATA6603 uses a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATA6602/ATA6603 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to ...
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... Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATA6602/ATA6603 uses a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. ...
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Comparison Between ATA6602/ATA6603 The ATA6602 and ATA6603 differ only in memory sizes, boot loader support, and interrupt vec- tor sizes. devices. Table 4-1. Device ATA6602 ATA6603 ATA6602 and ATA6603 support a real Read-While-Write Self-Programming mechanism. There is a separate ...
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Port C (PC5:0) Port 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The PC5..0 output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins ...
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About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all ...
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In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being ...
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ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate ...
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Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a ...
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Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in mapping them directly into the first 32 locations of the user Data Space. Although ...
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The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementa- tions of the AVR architecture is so small that ...
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Figure 4-6. 4.4.8 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which ...
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Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be ...
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AVR ATA6602/ATA6603 Memories This section describes the different memories in the ATA6602/ATA6603. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATA6602/ATA6603 features an EEPROM Memory for data storage. ...
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Figure 4-8. ATA6602/ATA6603 40 Program Memory Map, ATA6602/ATA6603 Program Memory Application Flash Section Boot Flash Section 0x0000 0x0FFF/0x1FFF 4921E–AUTO–09/09 ...
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SRAM Data Memory Figure 4-9 The ATA6602/ATA6603 is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from ...
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Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk Figure 4-10. On-chip Data SRAM Access Cycles 4.5.3 EEPROM Data Memory The ATA6602/ATA6603 ...
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The EEPROM Address Register – EEARH and EEARL Bit Read/Write Initial Value • Bits 15..9 – Res: Reserved Bits These bits are reserved bits in the ATA6602/ATA6603 and will always read as zero. • Bits 8..0 – EEAR8..0: EEPROM ...
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The Programming times for the different modes are shown in any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. Table 4-2. EEPM1 ...
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When the write access time has elapsed, the EEPE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted ...
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Assembly Code Example EEPROM_write: C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no ...
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Assembly Code Example EEPROM_read: C Code Example unsigned char EEPROM_read(unsigned int uiAddress 4.5.3.5 Preventing EEPROM Corruption During periods of low V too low for the CPU and the EEPROM to operate properly. These issues are the same as ...
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I/O Memory The I/O space definition of the ATA6602/ATA6603 is shown in 342. All ATA6602/ATA6603 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between ...
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System Clock and Clock Options 4.6.1 Clock Systems and their Distribution Figure 4-11 clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by ...
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Asynchronous Timer Clock – clk The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time ...
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Table 4-5. Typ Time-out (V Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum V delay will not monitor the actual voltage and it will be required to select a delay ...
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Table 4-6. Frequency Range Notes: The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in 4-7. Table 4-7. Oscillator Source/ Power Conditions Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Ceramic resonator, BOD ...
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Full Swing Crystal Oscillator Pins XTAL1 and XTAL2 are input and output, respectively inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in crystal or a ceramic resonator may be used. This ...
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Table 4-9. Oscillator Source/ Power Conditions Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Ceramic resonator, BOD enabled Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising power Crystal ...
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Calibrated Internal RC Oscillator The calibrated internal RC Oscillator by default provides a 8.0 MHz clock. The frequency is nom- inal value at 3V and 25°C. The device is shipped with the CKDIV8 Fuse programmed. See “System Clock Prescaler” ...
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Oscillator Calibration Register – OSCCAL Bit Read/Write Initial Value • Bits 7..0 – CAL7..0: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency. The ...
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Table 4-14. Power Conditions BOD enabled Fast rising power Slowly rising power Note: 4.6.8 External Clock The device can utilize a external clock source as shown in external clock, the CKSEL Fuses must be programmed as shown in Table 4-15. ...
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When applying an external clock required to avoid sudden changes in the applied clock fre- quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next ...
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To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within ...
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Table 4-17. CLKPS3 4.7 Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion ...
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Sleep Mode Control Register – SMCR The Sleep Mode Control Register contains control bits for power management. Bit Read/Write Initial Value • Bits 7..4 Res: Reserved Bits These bits are unused bits in the ATA6602/ATA6603, and will always read ...
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ADC Noise Reduction Mode When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the 2-wire Serial Interface address watch, ...
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Standby Mode When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept ...
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Power Reduction Register - PRR Bit Read/Write Initial Value • Bit 7 - PRTWI: Power Reduction TWI Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When waking up the ...
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Minimizing Power Consumption There are several possibilities to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected ...
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Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clk ...
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Reset Sources The ATA6602/ATA6603 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is ...
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Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply ...
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External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches ...
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Table 4-22. Symbol V HYST t BOD When the BOD is enabled, and V 4-19), the Brown-out Reset is immediately activated. When V level (V expired. The BOD circuit will only detect a drop in V ger than t Figure ...
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MCU Status Register – MCUSR The MCU Status Register provides information on which reset source caused an MCU reset. Bit Read/Write Initial Value • Bit 7..4: Res: Reserved Bits These bits are unused bits in the ATA6602/ATA6603, and will ...
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Table 4-23. Symbol Note: 4.8.9 Watchdog Timer ATA6602/ATA6603 has an Enhanced Watchdog Timer (WDT). The main features are: • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – ...
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In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake the device from sleep-modes, and also as a general system timer. One example is to limit the maximum time allowed for ...
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Assembly Code Example WDT_off: C Code Example void WDT_off(void Note: Note: ATA6602/ATA6603 74 (1) ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Clear WDRF in MCUSR in r16, MCUSR r16, (0xff & (0<<WDRF)) andi ...
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The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer. Assembly Code Example WDT_Prescaler_Change: C Code Example void WDT_Prescaler_Change(void Note: Note: The Watchdog Timer should be reset before ...
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Watchdog Timer Control Register - WDTCSR Bit Read/Write Initial Value • Bit 7 - WDIF: Watchdog Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF ...
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Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler and 0 The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The different prescaling values and their corresponding time-out periods are shown in ...
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Interrupt Vectors in ATA6602 Table 4-26. Reset and Interrupt Vectors in ATA6602 Program (2) Vector No. Address (1) 1 0x000 2 0x001 3 0x002 4 0x003 5 0x004 6 0x005 7 0x006 8 0x007 9 0x008 10 0x009 11 ...
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Table 4-27. BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATA6602 is: Address Labels Code 0x000 0x001 0x002 0x003 0x004 0x005 0x006 0x007 0X008 0x009 0x00A 0x00B 0x00C 0x00D 0x00E 0x00F ...
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When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and ...
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When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and ...
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Table 4-28. Reset and Interrupt Vectors in ATA6603 (Continued) Program (2) Vector No. Address 22 0x002A 23 0x002C 24 0x002E 25 0x0030 26 0x0032 Notes: Table 4-29 BOOTRST and IVSEL settings. If the program never enables an interrupt source, the ...
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The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATA6603 is: Address Labels Code 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 0x0016 0x0018 0x001A 0x001C 0x001E 0x0020 0x0022 0x0024 0x0026 ...
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When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and ...
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When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and ...
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Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is ...
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Figure 4-22. I/O Pin Equivalent Schematic All registers and bit references in this section are written in general form. A lower case “x” repre- sents the numbering letter for the port, and a lower case “n” represents the bit number. ...
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Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. tional description of one I/O-port pin, here generically called Pxn. Figure 4-23. General Digital I/O Note: 4.10.2.1 Configuring the Pin Each port pin consists ...
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Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 4.10.2.3 Switching Between ...
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Figure 4-24. Synchronization when Reading an Externally Applied Pin Value Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock ...
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The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned to port pins 6 and 7. The ...
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Digital Input Enable and Sleep Modes As shown in input of the Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, and Standby mode to avoid high ...
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Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. shows how the port pin control signals from the simplified ridden by alternate functions. The overriding signals may not be present in all ...
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Table 4-31 ure 4-26 on page 93 generated internally in the modules having the alternate function. Table 4-31. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for ...
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MCU Control Register – MCUCR Bit Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are ...
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The alternate pin configuration is as follows: • XTAL2/TOSC2/PCINT7 – Port B, Bit 7 XTAL2: Chip clock Oscillator pin 2. Used as clock pin for crystal Oscillator or Low-frequency crystal Oscillator. When used as a clock pin, the pin can ...
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MOSI/OC2/PCINT3 – Port B, Bit 3 MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB3. When ...
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Table 4-33. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Notes: Table 4-34. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATA6602/ATA6603 98 Overriding Signals for Alternate Functions in PB7..PB4 PB7/XTAL2/ PB6/XTAL1/ ...
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Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 4-35. Port Pin The alternate pin configuration is as follows: • RESET/PCINT14 – Port C, Bit 6 RESET, Reset pin: When the RSTDISBL ...
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SDA/ADC4/PCINT12 – Port C, Bit 4 SDA, 2-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PC4 is disconnected from the port and becomes the Serial Data I/O ...
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Table 4-36 shown in Table 4-36. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: Table 4-37. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 4921E–AUTO–09/09 and Table 4-37 relate the alternate ...
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Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 4-38. Port Pin The alternate pin configuration is as follows: • AIN1/OC2B/PCINT23 – Port D, Bit 7 AIN1, Analog Comparator Negative Input. Configure ...
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T1/OC0B/PCINT21 – Port D, Bit 5 T1, Timer/Counter1 counter source. OC0B, Output Compare Match output: The PD5 pin can serve as an external output for the Timer/Counter0 Compare Match B. The PD5 pin has to be configured as an ...
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Table 4-39 shown in Table 4-39. Signal Name PUOE PUO DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Table 4-40. Signal Name PUOE PUO DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATA6602/ATA6603 104 and Table 4-40 relate the alternate ...
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Register Description for I/O Ports 4.10.4.1 The Port B Data Register – PORTB Bit Read/Write Initial Value 4.10.4.2 The Port B Data Direction Register – DDRB Bit Read/Write Initial Value 4.10.4.3 The Port B Input Pins Address – PINB ...
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The Port D Data Direction Register – DDRD Bit Read/Write Initial Value 4.10.4.9 The Port D Input Pins Address – PIND Bit Read/Write Initial Value 4.11 External Interrupts The External Interrupts are triggered by the INT0 and INT1 pins ...
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External Interrupt Control Register A – EICRA The External Interrupt Control Register A contains control bits for interrupt sense control. Bit Read/Write Initial Value • Bit 7..4 – Res: Reserved Bits These bits are unused bits in the ATA6602/ATA6603, ...
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External Interrupt Mask Register – EIMSK Bit Read/Write Initial Value • Bit 7..2 – Res: Reserved Bits These bits are unused bits in the ATA6602/ATA6603, and will always read as zero. • Bit 1 – INT1: External Interrupt Request ...
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Pin Change Interrupt Control Register - PCICR Bit Read/Write Initial Value • Bit 7..3 - Res: Reserved Bits These bits are unused bits in the ATA6602/ATA6603, and will always read as zero. • Bit 2 - PCIE2: Pin Change ...
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Bit 0 - PCIF0: Pin Change Interrupt Flag 0 When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), ...
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Timer/Counter0 with PWM Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support. It allows accurate program execution timing (event man- agement) and wave generation. The main features are: • ...
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Definitions Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com- pare Unit, in this case ...
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Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 4-28 shows a block diagram of the counter and its surroundings. Figure 4-28. Counter Unit Block Diagram Signal description (internal signals): count direction clear ...
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Output Compare Unit The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers (OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a match. A match will set the Output Compare Flag (OCF0A or OCF0B) ...
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Compare Match Blocking by TCNT0 Write All CPU write operations to the TCNT0 Register will block any compare match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be ...
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The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or out- put) is still controlled by the Data Direction ...
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Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM02:0 = 2), the OCR0A Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the ...
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Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM02 provides a high fre- quency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. ...
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The PWM frequency for the output can be calculated by the following equation: f OCnxPWM The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A Register represents special cases when generating ...
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Figure 4-33. Phase Correct PWM Mode, Timing Diagram TCNTn OCn OCn Period The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches ...
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At the very start of period 2 in even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without Compare Match. • OCRnx changes ...
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Figure 4-36 mode and PWM mode, where OCR0A is TOP. Figure 4-36. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f clk (clk TCNTn OCRnx OCFnx Figure 4-37 mode where OCR0A is TOP. Figure 4-37. Timer/Counter Timing Diagram, Clear Timer ...
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Timer/Counter Register Description 4.12.8.1 Timer/Counter Control Register A – TCCR0A Bit Read/Write Initial Value • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of ...
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Table 4-46 rect PWM mode. Table 4-46. COM0A1 Note: • Bits 5:4 – COM0B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits ...
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Table 4-49 rect PWM mode. Table 4-49. COM0B1 Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the ATA6602/ATA6603 and will always read as zero. • Bits 1:0 – WGM01:0: ...
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Timer/Counter Control Register B – TCCR0B Bit Read/Write Initial Value • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future ...
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Table 4-51. CS02 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature ...
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Timer/Counter Interrupt Mask Register – TIMSK0 Bit Read/Write Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the ATA6602/ATA6603 and will always read as zero. • Bit 2 – OCIE0B: Timer/Counter Output Compare ...
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Bit 0 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hard- ware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic ...
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Figure 4-38. T1/T0 Pin Sampling The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated. Enabling and disabling of ...
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General Timer/Counter Control Register – GTCCR Bit Read/Write Initial Value • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the ...
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Figure 4-40. 16-bit Timer/Counter Block Diagram Note: 4.14.1.1 Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Regis- ter (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described ...
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The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Coun- ter value at all time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output ...
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Assembly Code Examples ... ; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ... C Code Examples unsigned int i; ... /* Set TCNT1 to 0x01FF */ ...
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Assembly Code Example TIM16_ReadTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ; Restore global interrupt flag out SREG,r18 ret C Code Example unsigned int TIM16_ReadTCNT1( void ) ...
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The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNT1: ; Save global interrupt ...
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Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits located in the Timer/Counter ...
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The counting sequence is determined by the setting of the Waveform Generation mode bits (WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B). There are close connections between how the counter behaves (counts) and how waveforms ...
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Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the low byte (ICR1L) and then the high byte (ICR1H). When the low byte is read the high byte is copied into the high byte ...
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Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended. Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. ...
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The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update ...
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Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the OC1x ...
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Compare Output Mode and Waveform Generation The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1 tells the Waveform Generator that no action on the OC1x Register ...
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Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM13 12), the OCR1A or ICR1 Register are used to manipulate the counter resolution. In CTC mode the counter is cleared ...
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Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM13 14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its ...
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The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addition the OC1A or ICF1 Flag is set at the same timer clock cycle as TOV1 is set when either OCR1A or ICR1 is used for ...
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A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OC1A to toggle its logical level on each compare match (COM1A1:0 = 1). This applies only if OCR1A is used to define ...
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Figure 4-47. Phase Correct PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set ...
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The PWM frequency for the output when using phase correct PWM can be calculated by the fol- lowing equation: f OCnxPCPWM The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x ...
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Figure 4-48. Phase and Frequency Correct PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ...
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The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal ...
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Figure 4-51 frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that ...
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Timer/Counter Register Description 4.14.10.1 Timer/Counter1 Control Register A – TCCR1A Bit Read/Write Initial Value • Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A • Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B The COM1A1:0 ...
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Table 4-55 correct or the phase and frequency correct, PWM mode. Table 4-55. COM1A1/COM1B1 Note: • Bit 1:0 – WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of ...
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Table 4-56. Waveform Generation Mode Bit Description WGM12 Mode WGM13 (CTC1) (PWM11 ...
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Bit 5 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCR1B is written. • Bit 4:3 – WGM13:2: Waveform Generation Mode See TCCR1A ...
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Timer/Counter1 – TCNT1H and TCNT1L Bit Read/Write Initial Value The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both ...
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Input Capture Register 1 – ICR1H and ICR1L Bit Read/Write Initial Value The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for ...
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Timer/Counter1 Interrupt Flag Register – TIFR1 Bit Read/Write Initial Value • Bit 7, 6 – Res: Reserved Bits These bits are unused bits in the ATA6602/ATA6603, and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, Input ...
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Timer/Counter2 with PWM and Asynchronous Operation Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width ...
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Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit reg- isters. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer ...
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Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 4-54 shows a block diagram of the counter and its surrounding environment. Figure 4-54. Counter Unit Block Diagram Signal description (internal signals): count direction ...
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Output Compare Unit The 8-bit comparator continuously compares TCNT2 with the Output Compare Register (OCR2A and OCR2B). Whenever TCNT2 equals OCR2A or OCR2B, the comparator signals a match. A match will set the Output Compare Flag (OCF2A or OCF2B) ...
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Compare Match Blocking by TCNT2 Write All CPU write operations to the TCNT2 Register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR2x to be ...
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Figure 4-56. Compare Match Output Unit, Schematic The general I/O port function is overridden by the Output Compare (OC2x) from the Waveform Generator if either of the COM2x1:0 bits are set. However, the OC2x pin direction (input or out- put) ...
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Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM22:0) and Compare Output mode (COM2x1:0) bits. The Compare Output mode ...
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An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to ...
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Figure 4-58. Fast PWM Mode, Timing Diagram TCNTn OCn OCn Period The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches TOP. If the inter- rupt is enabled, the interrupt handler routine can be used for updating the ...
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Phase Correct PWM Mode The phase correct PWM mode (WGM22 provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly ...
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In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM2x1:0 to ...
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Figure 4-61 Figure 4-61. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk I/O TCNTn TOVn Figure 4-62 Figure 4-62. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f (clk TCNTn OCRnx OCFnx Figure 4-63 Figure 4-63. Timer/Counter Timing Diagram, ...
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Timer/Counter Register Description 4.15.8.1 Timer/Counter Control Register A – TCCR2A Bit Read/Write Initial Value • Bits 7:6 – COM2A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC2A) behavior. If one or both of ...
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Table 4-60 rect PWM mode. Table 4-60. COM2A1 Note: • Bits 5:4 – COM2B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0 bits ...
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Table 4-63 rect PWM mode. Table 4-63. COM2B1 Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the ATA6602/ATA6603 and will always read as zero. • Bits 1:0 – WGM21:0: ...
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Timer/Counter Control Register B – TCCR2B Bit Read/Write Initial Value • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future ...
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Table 4-65. CS22 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature ...
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Timer/Counter2 Interrupt Mask Register – TIMSK2 Bit Read/Write Initial Value • Bit 2 – OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable When the OCIE2B bit is written to one and the I-bit in the Status Register is set ...
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Bit 0 – TOV2: Timer/Counter2 Overflow Flag The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic ...
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Write a value to TCCR2x, TCNT2, or OCR2x. b. Wait until the corresponding Update Busy Flag in ASSR returns to zero. c. Enter Power-save or ADC Noise Reduction mode. • When the asynchronous operation is selected, the 32.768 kHz ...
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Bit 5 – AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 ...
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Timer/Counter Prescaler Figure 4-64. Prescaler for Timer/Counter2 The clock source for Timer/Counter2 is named clk system I/O clock clk clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, ...
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Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATA6602/ATA6603 and peripheral devices or between several AVR devices. The ATA6602/ATA6603 SPI includes the following features: • Full-duplex, Three-wire Synchronous Data Transfer ...
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The interconnection between Master and Slave CPUs with SPI is shown in tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the ...
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In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the frequency of the SPI clock should never exceed f When the SPI is enabled, the ...
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Assembly Code Example SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi out ; Enable SPI, Master, set clock rate fck/16 ldi out ret SPI_MasterTransmit: ; Start transmission of data (r16) out Wait_Transmit: ; Wait for transmission complete ...
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The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: ; Set MISO output, all others input ldi out ; Enable SPI ldi out ret SPI_SlaveReceive: ...
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SS Pin Functionality 4.16.1.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so ...
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Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero configured as an input and is driven low while MSTR is set, ...
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SPI Status Register – SPSR Bit Read/Write Initial Value • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and ...
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Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in 4-67 and nal, ensuring sufficient time ...
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USART0 The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master ...
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Figure 4-69. USART Block Diagram Note: The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units. The Clock Generation ...
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Clock Generation The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn- chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in ...
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Table 4-71 ing the UBRRn value for each mode of operation using an internally generated clock source. Table 4-71. Operating Mode Asynchronous Normal mode (U2Xn = 0) Asynchronous Double Speed mode (U2Xn = 1) Synchronous Master mode Note: BAUD f ...
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External Clock External clocking is used by the synchronous slave modes of operation. The description in this section refers to External clock input from the XCKn pin is sampled by a synchronization register to minimize the chance of meta-stability. ...
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Frame Formats A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of the following as ...
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Parity Bit Calculation The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result of the exclusive or is inverted. The relation between the parity bit and data bits ...
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Assembly Code Example USART_Init: ; Set baud rate out out ; Enable receiver and transmitter ldi out ; Set frame format: 8data, 2stop bit ldi out ret C Code Example void USART_Init( unsigned int baud ) { /* Set baud ...
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Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxDn pin is overrid- den by ...
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Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZn = 7), the ninth bit must be written to the TXB8 bit in UCSRnB before the low byte of the character is written to UDRn. The following ...