ATA6603P-PLQW Atmel, ATA6603P-PLQW Datasheet - Page 34

MCU W/LIN TXRX REG WTCHDG 48-QFN

ATA6603P-PLQW

Manufacturer Part Number
ATA6603P-PLQW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet

Specifications of ATA6603P-PLQW

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATA6603P-PLQW
Manufacturer:
ATMEL
Quantity:
2 000
Part Number:
ATA6603P-PLQW
Manufacturer:
ATMEL/爱特梅尔
Quantity:
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4.4.5
34
ATA6602/ATA6603
General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve
the required performance and flexibility, the following input/output schemes are supported by the
Register File:
Figure 4-3
Figure 4-3.
• Bit 3 – V: Two’s Complement Overflow Flag
• Bit 2 – N: Negative Flag
• Bit 1 – Z: Zero Flag
• Bit 0 – C: Carry Flag
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Registers
Purpose
Working
General
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
“Instruction Set Description” for detailed information.
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruc-
tion Set Description” for detailed information.
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction
Set Description” for detailed information.
shows the structure of the 32 general purpose working registers in the CPU.
AVR CPU General Purpose Working Registers
7
R13
R14
R15
R16
R17
R26
R27
R28
R29
R30
R31
R0
R1
R2
...
...
0
Address
0x0D
0x0E
0x1A
0x1B
0x1C
0x1D
0x1E
0x00
0x01
0x02
0x0F
0x10
0x11
0x1F
X-register High Byte
Z-register High Byte
X-register Low Byte
Y-register High Byte
Y-register Low Byte
Z-register Low Byte
4921E–AUTO–09/09

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