ATA6603-EK Atmel, ATA6603-EK Datasheet
ATA6603-EK
Specifications of ATA6603-EK
Related parts for ATA6603-EK
ATA6603-EK Summary of contents
Page 1
... QFN48 Package 1. Description ATA6602/ATA6603 is a single-package dual-chip circuit family for LIN-bus slave node applications. It supports highly integrated solutions for in-vehicle LIN networks. The LIN-system-basis-chip (LIN-SBC) consists of a LIN transceiver, voltage regulator and window watchdog. The second chip is a microcontroller out of Atmel 8-bit microcontrollers with advanced RISC architecture ...
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... GND Ground 12 VCC Microcontroller supply voltage 13 GND Ground 14 VCC Microcontroller supply voltage 15 PB6 Port B 6 I/O line (TOSC1/XTAL1/PCINT6) 16 PB7 Port B 7 I/O line (TOSC2/XTAL2/PCINT7) 17 GND Ground 18 LIN LIN bus connection ATA6602/ATA6603 PC2 1 PC3 2 PC4 3 PC5 4 PC6 5 PD0 6 PD1 7 PD2 8 PD3 9 PD4 ...
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... Microcontroller ADC-unit supply voltage 43 ADC6 ADC input channel 6 44 AREF Analog reference voltage input 45 GND Ground 46 ADC7 ADC input channel 7 47 PC0 Port C 0 I/O line (ADC0/PCINT8) 48 PC1 Port C 1 I/O line (ADC1/PCINT9) Backside Heat slug is connected to GND 4921E–AUTO–09/09 ATA6602/ATA6603 3 ...
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... LIN bus systems. LIN-SBC is designed to handle the low speed data communica- tion in vehicles, for example, in convenience electronics. Improved slope control at the LIN driver ensures secure data communication kBaud. The bus output is capable of withstanding 60V. Sleep mode and Silent mode guarantee a very low current consumption. ATA6602/ATA6603 18V ± ...
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... TEMP GND 4921E–AUTO–09/09 Wake-up Bus Timer Slew Rate Control Control Unit Standby Mode Internal Testing Watchdog Unit MODE TM PTRIG ATA6602/ATA6603 Normal Mode Filter Short Circuit and Overtemperature Protection Normal Mode 5V ± 2%/50 mA Silent Mode 5V ± 7%/50 mA Undervoltage Reset OUT ...
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... This pin is the microcontroller interface to control the state of the LIN output. TXD must be pulled to ground in order to have the LIN bus low. If TXD is high, the LIN output transistor is turned off and the bus is in the recessive state, pulled up by the internal resistor. ATA6602/ATA6603 18V. After switching on VS, the IC starts with the S voltage ...
Page 7
... MODE to 5V and the watchdog is switched off. 3.3.13 TM Input Pin Pin TM is used in final production measurement at Atmel. In the application it is always con- nected to GND. 4921E–AUTO–09/09 regulator is also 50 mA, but the V DD ATA6602/ATA6603 > 6 ms, the DOM . The AC characteristics can 0V), RXD is switched off µA. The current VS tolerance is between 4 ...
Page 8
... Mode Select window (see two independent outputs can be used, or two outputs from the same microcontroller port; in the second case, the mode change is only one command. In Silent mode, the transmission path is disabled. Supply current from V The overall supply current from VDDs ATA6602/ATA6603 8 Unpowered Mode Batt a b ...
Page 9
... Figure 3-3. 4921E–AUTO–09/09 < 4.4V undervoltage condition occurs, the NRES is DDthS Switch to Silent Mode EN Mode Select window TXD t = 3.2 µs d NRES VCC Delay time Silent Mode t _sleep = maximum 15 µs d LIN LIN switches directly to recessive mode ATA6602/ATA6603 Figure 3-4 on page 10). Silent Mode 9 ...
Page 10
... The device switches from Sleep mode to Pre-normal bus mode. The VDD regulator is activated and the internal LIN slave termination resistor is switched on. The remote wake-up request is indicated by a low level at pin RXD to interrupt the microcon- troller (see ATA6602/ATA6603 10 LIN Wake-up Waveform Diagram from Silent Mode VLIN < 0 ...
Page 11
... If the device is switched into Sleep mode, V reset at pin NRES. Figure 3-5. 4921E–AUTO–09/09 Switch to Sleep Mode EN Mode Select window TXD t = 3.2 µs d NRES VCC Delay time Sleep Mode t _sleep = maximum 15 µs d LIN LIN switches directly to recessive mode ATA6602/ATA6603 ramps down without generating an undervoltage DD Sleep Mode 11 ...
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... The NRES is low for the reset time delay t 3.3.14.6 Debug Mode The watchdog is switched off with pin MODE high (5V) and in normal operation tied to GND. ATA6602/ATA6603 12 LIN Wake-up Waveform Diagram from Sleep Mode Low or floating Bus wake-up filtering time t ...
Page 13
... Transceiver VDD WD_OSC Off 5V 2. 2.5V Off 5V Off 0V to avoid resets at NRES (see D and Figure 3-4 on page 10). VS, a local wake-up is indicated after the time t Figure 3-7 on page ATA6602/ATA6603 TEMP RXD Figure 3-4 on page 10). ) ensures that no tran- WAKE to avoid resets at D 14). ...
Page 14
... The microcontroller can start its normal operation. • Pin EN provides a pull-down resistor to force the transceiver into recessive mode disconnected. • Pin RXD is connected with • Pin TXD provides a pull-up resistor to force the transceiver into recessive mode if TXD is disconnected. ATA6602/ATA6603 14 Wake Up Source Recognition VLIN < and S VLIN > ...
Page 15
... The main power dissipation of the IC is created from the V needed for the application. In Figure 3-9 on page 16 Figure 3-8. NRES 4921E–AUTO–09/09 you see the safe operating range of the LIN-SBC. VDD Voltage Regulator: Ramp Up and Undervoltage VS 12V 5.5V 3V VDD 5V V thun t vcc 5V ATA6602/ATA6603 output current res res_f , which is VDD ...
Page 16
... For example, with an external resistor of R watchdog come out as follows 12.5 µs due OSC t = 3922 800 840 157 nres After every reset the watchdog always starts with the lead time. ATA6602/ATA6603 16 Power Dissipation: Safe Operating Area versus V Voltage V at Different Ambient Temperatures ...
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... ATA6602/ATA6603 or wake up from Sleep mode, the 5V regulator is S (typically 10 ms), then it reset = 49 ms. After wake up from Silent mode the d starts immediately trigger 1 = 1.96 ms will reset the microcon- NRES have a fixed relationship with each other. A triggering ...
Page 18
... The sensor itself is built out of three diodes which are supplied by an internal BIAS current in Pre-normal mode and Normal mode. The typical voltage 27° cal negative temperature coefficient µA current source is switched off. Figure 3-11. Temperature Monitor ATA6602/ATA6603 18 = 14.2 ms (±15 application with R wd Table of Watchdog Timings ...
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... I –2 NRES –40 –150 –0.3 (1) T –40 case T – – – thjc R 35 thja 150 165 150 165 10 ATA6602/ATA6603 Max. Unit + +40 V +100 +6 +60 V +100 6.5 V +125 °C +150 °C +150 °C +125 °C 10 K/W K/W 170 ° ...
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... Low-level voltage input 4.2 High-level voltage input 4.3 Pull-down resistor V EN 4.4 Low-level input current Type means 100% tested 100% correlation tested Characterized on samples Design parameter ATA6602/ATA6603 20 Pin 28 >V – 0.5V 28 Bat < 14V (25°C to 125°C) < 14V (25°C to 125° ...
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... VDD > > > 5.5V 27 > 5.5V = 4.7 µF 27 < 18V S 27 < 5. > 3.3V – VDD 27 > 5.5 27 > 5.5V > ATA6602/ATA6603 Symbol Min. Typ. Max. V 4.5 NRESH V 0.2 NRESL 0.14 V 0.3 NRESLL reset t 3 res_f VDD 4.9 5.1 nor V VS VDD 5.1 low – ...
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... Receiver recessive state V EN 9.4 Receiver input hysteresis V HYS Wake detection LIN 9.5 High-level input voltage Wake detection LIN 9.6 Initializes a wake-up signal Low-level input voltage *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter ATA6602/ATA6603 22 Pin 500 = 18V 18 = 500 = 1000 ...
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... Bit / ( bus_rec(min) Bit = 0.422 VS; Rec(min) = 0.284 VS; Dom(min) = 7.0V to 18V µs Bit / ( bus_rec(max) Bit = 0V = max ( pdr rx_pdf = t – rx_pdr rx_pdf 30, 31 30, 31 30, 31 ATA6602/ATA6603 Symbol Min. Typ. Max 150 bus norm sleep dom D1 0.396 D2 0.581 t SLOPE_fall 3.5 22.5 t SLOPE_rise t 60 130 ...
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... S current 17 Mode Input Pin 17.1 Low-level voltage input 17.2 High-level voltage input High-level leakage V MODE 17.3 current V MODE *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter ATA6602/ATA6603 24 Pin = –250 µ 120 k OSC = ±3 µ ±3 µ ±3 µA ...
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... TH Rec(max Dom(max) (Transceiver supply of transmitting node) TH Rec(min) TH Dom(min) RXD (output of receiving node1) t rx_pdf(1) RXD (output of receiving node2) 4921E–AUTO–09/ Bit Bit t Bus_dom(max) LIN Bus Signal t Bus_dom(min) t rx_pdr(2) ATA6602/ATA6603 t Bit t Bus_rec(min) Thresholds of receiving node1 Thresholds of receiving node2 t Bus_rec(max) t rx_pdr(1) t rx_pdf(2) 25 ...
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... MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier • Non-volatile Program and Data Memories – 8/16 Kbytes of In-System Self-programmable Flash (ATA6602/ATA6603) Endurance: 75,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation – ...
Page 27
... Overview The ATA6602/ATA6603 uses a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATA6602/ATA6603 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 4.2.1 Block Diagram Figure 4-1 ...
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... ISO-TS-16949 grade 1. This data sheet con- tains limit values extracted from the results of extensive characterization (Temperature and Voltage). The quality and reliability of the ATA6602 and ATA6603 have been verified during reg- ular product qualification as per AEC-Q100. ...
Page 29
... Comparison Between ATA6602/ATA6603 The ATA6602 and ATA6603 differ only in memory sizes, boot loader support, and interrupt vec- tor sizes. devices. Table 4-1. Device ATA6602 ATA6603 ATA6602 and ATA6603 support a real Read-While-Write Self-Programming mechanism. There is a separate Boot Loader Section, and the SPM instruction can only execute from there. ...
Page 30
... ADC7:6 (TQFP and QFN Package Only) In the TQFP and QFN package, ADC7:6 serve as analog inputs to the A/D converter. These pins are powered from the analog supply and serve as 10-bit ADC channels. ATA6602/ATA6603 30 Table 4-3 on page , even if the ADC is not used. If the ADC is used, it should be connected ...
Page 31
... Instruction decoder Control lines 4921E–AUTO–09/09 Data Bus 8-bit Program Status counter and control 32 8 general purpose registers ALU DATA SRAM EEPROM I/O lines ATA6602/ATA6603 Interrupt unit SPI unit Watchdog timer Analog comparator I/O Module 1 I/O Module 2 I/O Module n 31 ...
Page 32
... SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATA6602/ATA6603 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...
Page 33
... Bit 4 – S: Sign Bit The S-bit is always an exclusive or between the Negative Flag N and the Two’s Comple- ment Overflow Flag V. See the “Instruction Set Description” for detailed information. 4921E–AUTO–09/ R/W R/W R/W R ATA6602/ATA6603 R/W R/W R/W R SREG 33 ...
Page 34
... Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 4-3 Figure 4-3. General Purpose Working Registers ATA6602/ATA6603 34 shows the structure of the 32 general purpose working registers in the CPU. AVR CPU General Purpose Working Registers ...
Page 35
... Stack with return from subroutine RET or return from interrupt RETI. 4921E–AUTO–09/09 Figure 4-3 on page 34, each register is also assigned a data memory address, The X-, Y-, and Z-registers R27 (0x1B R29 (0x1D R31 (0x1F) ATA6602/ATA6603 Figure 4- R26 (0x1A R28 (0x1C R30 (0x1E ...
Page 36
... MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 4-5. Figure 4-6 on page 37 cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. ATA6602/ATA6603 SP15 ...
Page 37
... The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse (see and ATA6603” on page When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – ...
Page 38
... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. ATA6602/ATA6603 38 ; store SREG value ; disable interrupts during timed sequence ...
Page 39
... Since all AVR instructions are bits wide, the Flash is organized as 2/4/8K x 16. For software security, the Flash Program memory space is divided into two sec- tions, Boot Loader Section and Application Program Section in ATA6602 and ATA6603. See SELFPRGEN description in section SPMCSR” ...
Page 40
... Figure 4-8. ATA6602/ATA6603 40 Program Memory Map, ATA6602/ATA6603 Program Memory Application Flash Section Boot Flash Section 0x0000 0x0FFF/0x1FFF 4921E–AUTO–09/09 ...
Page 41
... SRAM Data Memory Figure 4-9 The ATA6602/ATA6603 is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used ...
Page 42
... EEPROM Data Memory The ATA6602/ATA6603 contains 512 bytes of data EEPROM memory organized as a sep- arate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...
Page 43
... Initial Value • Bits 7..6 – Res: Reserved Bits These bits are reserved bits in the ATA6602/ATA6603 and will always read as zero • Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE ...
Page 44
... Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to pro- gram the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader Support – Read-While-Write Self-Programming, ATA6602 and ATA6603” on page 282 Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out ...
Page 45
... Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish. 4921E–AUTO–09/09 EEPROM Programming Time Number of Calibrated RC Oscillator Cycles 26,368 ATA6602/ATA6603 Table 4-3 lists the typical Typ Programming Time 3 ...
Page 46
... The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. ATA6602/ATA6603 46 ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r18:r17) in address register ...
Page 47
... Wait for completion of previous write */ while(EECR & (1<<EEPE Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from Data Register */ return EEDR; the EEPROM data can be corrupted because the supply voltage is CC, ATA6602/ATA6603 reset Protection circuit can CC 47 ...
Page 48
... The I/O space definition of the ATA6602/ATA6603 is shown in 342. All ATA6602/ATA6603 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...
Page 49
... Control Unit clk ASY System Clock Prescaler Source clock Clock Multiplexer Timer/Counter External Clock Oscillator is halted, TWI address recognition in all sleep modes. I/O ATA6602/ATA6603 CPU Core RAM ADC clk CPU clk FLASH Reset Logic Watchdog Timer Watchdog clock Watchdog Oscillator Crystal ...
Page 50
... Watchdog Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The selectable delays are shown in Watchdog Oscillator is voltage dependent as shown in ATA6602/ATA6603 50 ASY Device Clocking Options Select 1. For all fuses “1” means unprogrammed while “0” means programmed. ...
Page 51
... Number of Watchdog Oscillator Cycles = 5.0V) Typ Time-out ( 4 53. Table 4-6 on page C2 C1 52. ATA6602/ATA6603 = 3.0V) Number of Cycles 4 before it releases the reset, and the time-out delay CC Figure 4-12. Either a quartz crystal or a 52. For ceramic resonators, the capacitor val- XTAL2 XTAL1 ...
Page 52
... Ceramic resonator, slowly rising power Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power Notes: ATA6602/ATA6603 52 Low Power Crystal Oscillator Operating Modes (1) (MHz) CKSEL3..1 0.4 - 0.9 0.9 - 3.0 3.0 - 8.0 8.0 - 16.0 1. The frequency ranges are preliminary values. Actual values are TBD. ...
Page 53
... If 8 MHz frequency exceeds the specification of the device (depends on V Fuse can be programmed in order to divide the internal frequency must be ensured that the resulting divided clock meets the frequency specification of the device ATA6602/ATA6603 Figure 4-12 on page 51. Note that the Full Swing Crystal 54. For ceramic resonators, the capacitor val- Table ...
Page 54
... Table 4-10. Power Conditions BOD enabled Fast rising power Slowly rising power BOD enabled Fast rising power Slowly rising power Note: ATA6602/ATA6603 54 Start-up Times for the Full Swing Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save 258 CK 258 ...
Page 55
... Power-down and Power-save Reserved 1. If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4 ensure programming mode can be entered. The device is shipped with this option selected. 2. ATA6602/ATA6603 Table 4-11. If selected, it will operate with “Calibration Byte” (1)(3) CKSEL3..0 0010 ), the CKDIV8 CC ...
Page 56
... C. This clock may be select as the system clock by programming the CKSEL Fuses to “11” as shown in Table 4-13. Note: When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 4-14 on page ATA6602/ATA6603 CAL7 CAL6 ...
Page 57
... NC EXTERNAL CLOCK SIGNAL Start-up Times for the External Clock Selection Start-up Time from Power-down and Power-save Reserved ATA6602/ATA6603 Additional Delay from Reset (1) 14CK 14CK + 4 ms 14CK + 64 ms Figure 4-14. To run the device on an Table 4-15. (2) ...
Page 58
... System Clock Prescaler The ATA6602/ATA6603 has a system clock prescaler, and the system clock can be divided by setting the decrease the system clock frequency and the power consumption when the requirement for pro- cessing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals ...
Page 59
... The device is shipped with the CKDIV8 Fuse programmed. 4921E–AUTO–09/ CLKPCE – – – R Table 4-17 on page 60. ATA6602/ATA6603 CLKPS3 CLKPS2 CLKPS1 CLKPS0 R/W R/W R/W R/W See Bit Description CLKPR 59 ...
Page 60
... The figure is helpful in selecting an appropriate sleep mode. ATA6602/ATA6603 60 Clock Prescaler Select CLKPS2 CLKPS1 presents the different clock systems in the ATA6602/ATA6603, and their CLKPS0 Clock Division Factor Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved Table 4-18 on page 61 for a summary enabled 128 256 4921E–AUTO–09/09 ...
Page 61
... Initial Value • Bits 7..4 Res: Reserved Bits These bits are unused bits in the ATA6602/ATA6603, and will always read as zero. • Bits 3..1 – SM2..0: Sleep Mode Select Bits 2, 1, and 0 These bits select between the five available sleep modes as shown in Table 4-18 ...
Page 62
... If Timer/Counter2 is not using the asynchronous clock, the Timer/Counter Oscillator is stopped during sleep. If Timer/Counter2 is not using the synchronous clock, the clock source is stopped during sleep. Note that even if the synchronous clock is running in Power-save, this clock is only available for Timer/Counter2. ATA6602/ATA6603 62 , clk , and clk ...
Page 63
... Active Clock Domains and Wake-up Sources in the Different Sleep Modes Active Clock Domains (1) 1. Only recommended with external crystal or resonator selected as clock source Timer/Counter2 is running in asynchronous mode. 3. For INT1 and INT0, only level interrupt. “Power-down Supply Current” on page 328 ATA6602/ATA6603 Oscillators Wake-up Sources ( (2) ( ...
Page 64
... Timer/Counter0 is enabled, operation will continue like before the shutdown. • Bit 4 - Res: Reserved bit This bit is reserved in ATA6602/ATA6603 and will always read as zero. • Bit 3 - PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown. • ...
Page 65
... Comparator” on page 260 for details on the start-up time. “Watchdog Timer” on page 72 for details on how to configure the Watchdog Timer. ATA6602/ATA6603 “Analog-to-Digital Converter” on page 263 for details on how to configure the Analog “Brown-out Detection” on page 69 “Internal Volt- ...
Page 66
... During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. For the ATA6603, the instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. For the ATA6602, the instruc- tion placed at the Reset Vector must be an RJMP – ...
Page 67
... Reset Sources The ATA6602/ATA6603 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. ...
Page 68
... VCC Rise Rate to ensure Power-on Reset CCRR V RESET Pin Threshold Voltage RST Note: 1. Before rising, the supply has to be between ATA6602/ATA6603 68 Table 4-20. The POR is activated whenever V rise. The RESET signal is activated again, without any delay, CC decreases below the detection level. ...
Page 69
... V antees that a Brown-Out Reset will occur before V operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 110 and BODLEVEL = 101 for ATA6602V/ATA6603V, and BODLEVEL = 101 ATA6602/ATA6603 and BODLEVEL = 101 for ATA6602/ATA6603 68) will generate a reset, even if the clock is not – ...
Page 70
... Time-out period t “Watchdog Timer” on page 72 Figure 4-20. Watchdog System Reset During Operation RESET TIME-OUT RESET TIME-OUT INTERNAL RESET ATA6602/ATA6603 70 Brown-out Characteristics Parameter Brown-out Detector Hysteresis Min Pulse Width on Brown-out Reset decreases to a value below the trigger level ( ...
Page 71
... Initial Value • Bit 7..4: Res: Reserved Bits These bits are unused bits in the ATA6602/ATA6603, and will always read as zero. • Bit 3 – WDRF: Watchdog System Reset Flag This bit is set if a Watchdog System Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • ...
Page 72
... Note: 4.8.9 Watchdog Timer ATA6602/ATA6603 has an Enhanced Watchdog Timer (WDT). The main features are: • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from • Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode Figure 4-21 ...
Page 73
... The following code example shows one assembly and one C function for turning off the Watch- dog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions. 4921E–AUTO–09/09 ATA6602/ATA6603 73 ...
Page 74
... Assembly Code Example WDT_off: C Code Example void WDT_off(void Note: Note: ATA6602/ATA6603 74 (1) ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Clear WDRF in MCUSR in r16, MCUSR r16, (0xff & (0<<WDRF)) andi MCUSR, r16 out ; Write logical one to WDCE and WDE ...
Page 75
... Turn on global interrupt sei ret (1) __disable_interrupt(); __watchdog_reset(); /* Start timed equence */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Set new prescaler(time-out) value = 64K cycles (~0 WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0); __enable_interrupt(); 1. The example code assumes that the part specific header file is included. ATA6602/ATA6603 75 ...
Page 76
... Bit 3 - WDE: Watchdog System Reset Enable WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets dur- ing conditions causing failure, and a safe start-up after the failure. ATA6602/ATA6603 ...
Page 77
... Each Interrupt Vector occupies two instruction words in ATA6603, and one instruction word in ATA6602. • In ATA6602 and ATA6603, the Reset Vector is affected by the BOOTRST fuse, and the Interrupt Vector start address is affected by the IVSEL bit in MCUCR. 4921E–AUTO–09/09 4-25. ...
Page 78
... When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset (see “Boot Loader Support – Read-While-Write Self-Programming, ATA6602 and ATA6603” on page 282). 2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section ...
Page 79
... SPH,r16 ldi r16, low(RAMEND) out SPL,r16 sei <instr> xxx ... ... ... ATA6602/ATA6603 (1) Interrupt Vectors Start Address 0x001 Boot Reset Address + 0x001 0x001 Boot Reset Address + 0x001 Table 4-107 on page 296. For the BOOTRST Fuse “1” Comments ; Reset Handler ; IRQ0 Handler ; IRQ1 Handler ...
Page 80
... Reset and Interrupt Vector Addresses in ATA6602 is: Address Labels Code .org 0x001 0x001 0x002 ... 0x019 ; .org 0xC00 0xC00 0xC01 0xC02 0xC03 0xC04 0xC05 ATA6602/ATA6603 80 RESET: ldi r16,high(RAMEND); Main program start out SPH,r16 ldi r16,low(RAMEND) out SPL,r16 sei <instr> xxx rjmp EXT_INT0 ...
Page 81
... Reset and Interrupt Vector Addresses in ATA6602 is: Address Labels Code ; .org 0xC00 0xC00 0xC01 0xC02 ... 0xC19 ; 0xC1A 0xC1B 0xC1C 0xC1D 0xC1E 0xC1F 4.9.2 Interrupt Vectors in ATA6603 Table 4-28. Reset and Interrupt Vectors in ATA6603 Program (2) Vector No. Address (1) 1 0x0000 2 0x0002 3 0x0004 4 0x0006 5 0x0008 6 0x000A 7 ...
Page 82
... When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section. shows reset and Interrupt Vectors placement for the various combinations of Reset and Interrupt Vectors Placement in ATA6603 IVSEL Reset Address 1 ...
Page 83
... The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATA6603 is: Address Labels Code 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 0x0016 0x0018 0x001A 0x001C 0x001E 0x0020 0x0022 0x0024 0x0026 0x0028 0x002A 0x002C ...
Page 84
... When the BOOTRST Fuse is programmed and the Boot section size set to 2K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATA6603 is: Address Labels Code .org 0x0002 0x0002 0x0004 ... ...
Page 85
... When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATA6603 is: Address Labels Code ...
Page 86
... The pin driver is strong enough to drive LED displays directly. All port pins have indi- vidually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both V “Electrical Characteristics” on page 318 ATA6602/ATA6603 86 ; Enable change of Interrupt Vectors ldi r16, (1<<IVCE) out MCUCR, r16 ...
Page 87
... Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 4921E–AUTO–09/09 Pxn C pin “Register Description for I/O Ports” on page 93. Refer to the individual module sections for a full description of the alter- ATA6602/ATA6603 R pu Logic See Figure "General Digital I/O" for Details 105. ...
Page 88
... If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). ATA6602/ATA6603 88 (1) Pxn ...
Page 89
... Input 1 1 Input 0 X Output 1 X Output Figure 4-23 on page shows a timing diagram of the synchronization when reading an externally applied pin ATA6602/ATA6603 Pull-up Comment No Tri-state (Hi-Z) Yes Pxn will source current if ext. pulled low. No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) ...
Page 90
... When reading back a software assigned pin value, a nop instruction must be inserted as indi- cated in the clock. In this case, the delay tpd through the synchronizer is 1 system clock period. Figure 4-25. Synchronization when Reading a Software Assigned Pin Value ATA6602/ATA6603 90 SYSTEM CLK INSTRUCTIONS XXX ...
Page 91
... Read port pins */ i = PINB; ... 1. For the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. ATA6602/ATA6603 91 ...
Page 92
... In this case, the pull-up will be disabled during reset. If low power consumption during reset is important recommended to use an external pull-up or pull-down. Connecting unused pins directly to V accidentally configured as an output. ATA6602/ATA6603 92 Figure 4-23 on page 88, the digital input signal can be clamped to ground at the “Alternate Port Functions” on page ...
Page 93
... Pxn, PORT TOGGLE OVERRIDE ENABLE 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. All other signals are unique for each pin. ATA6602/ATA6603 Figure 4-23 on page 88 PUD ...
Page 94
... The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. ATA6602/ATA6603 94 summarizes the function of the overriding signals. The pin and port indexes from are not shown in the succeeding tables. The overriding signals are ...
Page 95
... SS (SPI Bus Master Slave select) OC1B (Timer/Counter1 Output Compare Match B Output) PCINT2 (Pin Change Interrupt 2) OC1A (Timer/Counter1 Output Compare Match A Output) PCINT1 (Pin Change Interrupt 1) ICP1 (Timer/Counter1 Input Capture Input) CLKO (Divided System Clock Output) PCINT0 (Pin Change Interrupt 0) ATA6602/ATA6603 – – IVSEL ...
Page 96
... SPI is enabled as a Slave, the data direction of this pin is controlled by DDB4. When the pin is forced by the SPI input, the pull-up can still be controlled by the PORTB4 bit. PCINT4: Pin Change Interrupt source 4. The PB4 pin can serve as an external interrupt source. ATA6602/ATA6603 96 4921E–AUTO–09/09 ...
Page 97
... Table 4-33 on page 98 the overriding signals shown in OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. 4921E–AUTO–09/09 ATA6602/ATA6603 and Table 4-34 on page 98 relate the alternate functions of Port B to Figure 4-26 on page 93. SPI MSTR INPUT and SPI SLAVE ...
Page 98
... DIEOV DI AIO Notes: Table 4-34. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATA6602/ATA6603 98 Overriding Signals for Alternate Functions in PB7..PB4 PB7/XTAL2/ PB6/XTAL1/ (1) TOSC2/PCINT7 TOSC1/PCINT6 INTRC • EXTCK+ INTRC + AS2 AS2 0 0 INTRC • EXTCK+ INTRC + AS2 AS2 0 ...
Page 99
... PCINT12 (Pin Change Interrupt 12) ADC3 (ADC Input Channel 3) PC3 PCINT11 (Pin Change Interrupt 11) ADC2 (ADC Input Channel 2) PC2 PCINT10 (Pin Change Interrupt 10) ADC1 (ADC Input Channel 1) PC1 PCINT9 (Pin Change Interrupt 9) ADC0 (ADC Input Channel 0) PC0 PCINT8 (Pin Change Interrupt 8) ATA6602/ATA6603 Table 4-35. 99 ...
Page 100
... PCINT9: Pin Change Interrupt source 9. The PC1 pin can serve as an external interrupt source. • ADC0/PCINT8 – Port C, Bit 0 PC0 can also be used as ADC input Channel 0. Note that ADC input channel 0 uses analog power. PCINT8: Pin Change Interrupt source 8. The PC0 pin can serve as an external interrupt source. ATA6602/ATA6603 100 4921E–AUTO–09/09 ...
Page 101
... PCINT11 • PCIE1 + PCINT10 • PCIE1 + ADC3D ADC2D PCINT11 • PCIE1 PCINT10 • PCIE1 PCINT11 INPUT PCINT10 INPUT ADC3 INPUT ADC2 INPUT ATA6602/ATA6603 (1) PC4/SDA/ADC4/PCINT12 TWEN PORTC4 • PUD TWEN SDA_OUT TWEN 0 PCINT12 • PCIE1 + ADC4D PCINT12 • PCIE1 PCINT12 INPUT ...
Page 102
... The OC0A pin is also the output pin for the PWM mode timer function. PCINT22: Pin Change Interrupt source 22. The PD6 pin can serve as an external interrupt source. ATA6602/ATA6603 102 Port D Pins Alternate Functions Alternate Function AIN1 (Analog Comparator Negative Input) ...
Page 103
... DDD0. When the USART forces this pin input, the pull-up can still be controlled by the PORTD0 bit. PCINT16: Pin Change Interrupt source 16. The PD0 pin can serve as an external interrupt source. 4921E–AUTO–09/09 ATA6602/ATA6603 103 ...
Page 104
... Table 4-40. Signal Name PUOE PUO DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATA6602/ATA6603 104 and Table 4-40 relate the alternate functions of Port D to the overriding signals Figure 4-26 on page 93. Overriding Signals for Alternate Functions PD7..PD4 PD7/AIN1 PD6/AIN0/ /PCINT23 OC0A/PCINT22 0 ...
Page 105
... DDC6 DDC5 DDC4 R R/W R/W R – PINC6 PINC5 PINC4 N/A N/A N PORTD7 PORTD6 PORTD5 PORTD4 R/W R/W R/W R ATA6602/ATA6603 PORTB3 PORTB2 PORTB1 PORTB0 R/W R/W R/W R DDB3 DDB2 DDB1 DDB0 R/W R/W R/W R PINB3 PINB2 PINB1 PINB0 N/A N/A ...
Page 106
... MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter- rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page ATA6602/ATA6603 106 ...
Page 107
... Initial Value • Bit 7..4 – Res: Reserved Bits These bits are unused bits in the ATA6602/ATA6603, and will always read as zero. • Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the cor- responding interrupt mask are set ...
Page 108
... Initial Value • Bit 7..2 – Res: Reserved Bits These bits are unused bits in the ATA6602/ATA6603, and will always read as zero. • Bit 1 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled ...
Page 109
... Initial Value • Bit 7..3 - Res: Reserved Bits These bits are unused bits in the ATA6602/ATA6603, and will always read as zero. • Bit 2 - PCIE2: Pin Change Interrupt Enable 2 When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 2 is enabled ...
Page 110
... Initial Value • Bit 7 – Res: Reserved Bit This bit is an unused bit in the ATA6602/ATA6603, and will always read as zero. • Bit 6..0 – PCINT14..8: Pin Change Enable Mask 14..8 Each PCINT14..8-bit selects whether pin change interrupt is enabled on the corresponding I/O pin ...
Page 111
... Direction TN Prescaler TOP BOTTOM = = 0 OCnA (Int.Req.) Waveform Generation Fixed OCnB TOP (Int.Req.) Value Waveform Generation TCCRnB ATA6602/ATA6603 Figure 4-27. The device-spe- “8-bit Timer/Counter Register Description” on must be written to zero to TOVn (Int.Req.) TOSC1 T/C Oscillator TOSC2 clk I/O OCnA OCnB 111 ...
Page 112
... The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits located in the Timer/Counter Control Register (TCCR0B). For details on clock sources and pres- caler (see ATA6602/ATA6603 112 Table 4-43 are also used extensively throughout the document. ...
Page 113
... Signalize that TCNT0 has reached maximum value. Signalize that TCNT0 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T0 116). ATA6602/ATA6603 TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ...
Page 114
... Force Output Compare (FOC0x) bit. Forcing compare match will not set the OCF0x Flag or reload/clear the timer, but the OC0x pin will be updated real compare match had occurred (the COM0x1:0 bits settings define whether the OC0x pin is set, cleared or toggled). ATA6602/ATA6603 114 shows a block diagram of the Output Compare unit. DATA BUS ...
Page 115
... OC0x Register, not the OC0x pin system reset occur, the OC0x Register is reset to “0”. Figure 4-30. Compare Match Output Unit, Schematic 4921E–AUTO–09/09 COMnx1 Waveform COMnx0 D Generator FOCnx D PORT D clk I/O ATA6602/ATA6603 Figure 4-30 shows a simplified Q 1 OCnx DDR OCnx Pin 115 ...
Page 116
... The Output Compare unit can be used to generate interrupts at some given time. Using the Out- put Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. ATA6602/ATA6603 116 “8-bit Timer/Counter Register Description” on page Table 4-44 on page “ ...
Page 117
... As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 4921E–AUTO–09/09 TCNTn OCn (Toggle Period f clk_I/O ------------------------------------------------------ - N OCRnx ATA6602/ATA6603 Figure 4-31. The counter value (TCNT0) OCnx Interrupt Flag Set (COMnx1 OC0 117 ...
Page 118
... OC0x Register at the compare match between OCR0x and TCNT0, and clearing (or setting) the OC0x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). ATA6602/ATA6603 118 Figure 4-32. The TCNT0 value is in the timing diagram shown as a his- ...
Page 119
... The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0x and TCNT0. 4921E–AUTO–09/09 f clk_I/O = -------------------- - N 256 120. The TCNT0 value is in the timing diagram shown as a histogram for ATA6602/ATA6603 = f /2 when OCR0A is set to zero. This OC0 clk_I/O 119 ...
Page 120
... PWM mode. If the OCR0A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. ATA6602/ATA6603 120 1 ...
Page 121
... Timer/Counter operation. The figure clk I/O TN /1) MAX - 1 shows the same timing data, but with the prescaler enabled. I/O TN /8) MAX - 1 ATA6602/ATA6603 OCnx has a transition from high to low Figure 4-33 on page 120. When the OCR0A ) is therefore shown MAX BOTTOM /8) clk_I/O MAX ...
Page 122
... OCR0A is TOP. Figure 4-37. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Pres- clkTN (clk TCNTn (CTC) OCRnx OCFnx ATA6602/ATA6603 122 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC I/O clk Tn /8) I/O OCRnx - 1 ...
Page 123
... Clear OC0A on Compare Match, set OC0A at TOP 1 Set OC0A on Compare Match, clear OC0A at TOP 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at TOP. See for more details. ATA6602/ATA6603 – ...
Page 124
... Table 4-48 mode. Table 4-48. COM0B1 Note: ATA6602/ATA6603 124 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase cor- Compare Output Mode, Phase Correct PWM Mode COM0A0 Description 0 Normal port operation, OC0A disconnected. WGM02 = 0: Normal Port Operation, OC0A Disconnected. ...
Page 125
... Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the ATA6602/ATA6603 and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the count- ...
Page 126
... OCR0B as TOP. The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATA6602/ATA6603 and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the • Bits 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter ...
Page 127
... I External clock source on T0 pin. Clock on falling edge External clock source on T0 pin. Clock on rising edge R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R ATA6602/ATA6603 TCNT0[7:0] R/W R/W R OCR0A[7:0] R/W R/W R OCR0B[7:0] R/W R/W R TCNT0 R/W ...
Page 128
... Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the ATA6602/ATA6603 and will always read as zero. • Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled ...
Page 129
... Alternatively, one of four taps from the prescaler can be used as a CLK_I/O ). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization T0 shows a functional equivalent block diagram of the T1/T0 synchronization and /clk T1 ATA6602/ATA6603 Table 4-50 on page 125. /8, f CLK_I/O CLK_I/O pulse for each positive (CSn2 negative ...
Page 130
... Oscillator source (crystal, resonator, and capacitors) tolerances recommended that maximum frequency of an external clock source is less than f An external clock source can not be prescaled. Figure 4-39. Prescaler for Timer/Counter0 and Timer/Counter1 clk PSRSYNC CS10 CS11 CS12 Note: ATA6602/ATA6603 130 clk I/O Synchronization < ...
Page 131
... Description” on page The PRTIM1 bit in enable Timer/Counter1 module. 4921E–AUTO–09/ TSM – – – R 153. “Power Reduction Register - PRR” on page 64 ATA6602/ATA6603 – – PSRASY PSRSYNC R R R/W R Figure 4-40 on page “16-bit Timer/Counter Register must be written to zero to GTCCR 132. The ...
Page 132
... T1 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk ATA6602/ATA6603 132 Count ...
Page 133
... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF the value stored in the OCR1A or ICR1 Register. The assignment is depen- dent of the mode of operation. ATA6602/ATA6603 “Out- 133 ...
Page 134
... The following code examples show how atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. ATA6602/ATA6603 134 (1) (1) 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, “ ...
Page 135
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATA6602/ATA6603 135 ...
Page 136
... If writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case. ATA6602/ATA6603 136 (1) (1) 1 ...
Page 137
... Signalize that TCNT1 has reached minimum value (zero). ). The clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear ATA6602/ATA6603 129). TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic (From Prescaler) ...
Page 138
... TCNT1 value is copied into ICR1 Register. If enabled (ICIE1 = 1), the Input Capture Flag generates an Input Capture interrupt. The ICF1 Flag is automatically cleared when the interrupt is executed. Alternatively the ICF1 Flag can be cleared by software by writing a logical one to its I/O bit location. ATA6602/ATA6603 138 “Modes of Operation” on page DATA BUS (8-bit) ...
Page 139
... Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. 4921E–AUTO–09/09 133. ATA6602/ATA6603 “Accessing 16-bit Registers” Figure 4-38 on page 130). The edge detector is 139 ...
Page 140
... Compare unit (A/B). The elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded. Figure 4-43. Output Compare Unit, Block Diagram ATA6602/ATA6603 140 “Modes of Operation” on page shows a block diagram of the Output Compare unit. The small “n” in the register and ...
Page 141
... Normal mode. The OC1x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. 4921E–AUTO–09/09 133. ATA6602/ATA6603 “Accessing 16-bit Registers” 141 ...
Page 142
... The design of the Output Compare pin logic allows initialization of the OC1x state before the out- put is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of operation (see The COM1x1:0 bits have no effect on the Input Capture unit. ATA6602/ATA6603 142 COMnx1 Waveform ...
Page 143
... Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 4921E–AUTO–09/09 Table 4-53 on page “Compare Match Output Unit” on page “Timer/Counter Timing Diagrams” on page ATA6602/ATA6603 153. For fast PWM mode refer to 142). Table 4-54 on Table 4-55 on 151. ...
Page 144
... OCnA The N variable represents the prescaler factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV1 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x0000. ATA6602/ATA6603 144 TCNTn OCnA (Toggle ...
Page 145
... Figure 4-46. Fast PWM Mode, Timing Diagram 4921E–AUTO–09/09 TOP log + 1 = ---------------------------------- - log 2 TCNTn OCnx OCnx Period ATA6602/ATA6603 Figure OCRnx/TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnx1 (COMnx1 4-46. The figure 145 ...
Page 146
... PWM mode. If the OCR1x is set equal to BOTTOM (0x0000) the out- put will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCR1x equal to TOP will result in a constant high or low output (depending on the polarity of the output set by the COM1x1:0 bits). ATA6602/ATA6603 146 f clk_I/O ...
Page 147
... TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. 4921E–AUTO–09/ when OCR1A is set to zero (0x0000). This feature clk_I/O TOP log ---------------------------------- - log 2 ATA6602/ATA6603 Figure 4-47 on page 147 ...
Page 148
... The PWM waveform is generated by setting (or clearing) the OC1x Register at the compare match between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OC1x Register at compare match between OCR1x and TCNT1 when the counter decrements. ATA6602/ATA6603 148 TCNTn OCnx ...
Page 149
... OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. 4921E–AUTO–09/09 f clk_I/O = --------------------------------- N TOP 2 and Figure 4-48 on page 150). TOP log + 1 = ---------------------------------- - log 2 Figure 4-48 on page ATA6602/ATA6603 Figure 4-47 150. The figure shows phase and fre- 149 ...
Page 150
... OC1x Register at compare match between OCR1x and TCNT1 when the counter decrements. The PWM frequency for the output when using phase and frequency correct PWM can be calculated by the following equation: f OCnxPFCPWM The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). ATA6602/ATA6603 150 TCNTn OCnx OCnx 1 ...
Page 151
... OCFnx shows the same timing data, but with the prescaler enabled. clk I/O clkTn (clk /8) I/O TCNTn OCRnx - 1 OCRnx OCFnx ATA6602/ATA6603 ) is therefore shown shows a timing diagram for the setting of OCF1x. OCRnx OCRnx + 1 OCRnx Value OCRnx OCRnx + 1 OCRnx Value OCRnx + 2 /8) clk_I/O ...
Page 152
... TOP) Figure 4-52 Figure 4-52. Timer/Counter Timing Diagram, with Prescaler (f (CTC and FPWM) (PC and PFC PWM) TOVn (FPWM) and ICFn (if used (Update at TOP) ATA6602/ATA6603 152 shows the count sequence close to TOP in various modes. When using phase and clk I/O clk Tn (clk ...
Page 153
... COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast Compare Output Mode, Fast PWM COM1A0/COM1B0 special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the compare match is ignored, but the set or clear is done at TOP. See Mode” on page 145 for more details. ATA6602/ATA6603 – – WGM11 R R ...
Page 154
... Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes (see of Operation” on page ATA6602/ATA6603 154 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase ...
Page 155
... PWM, Phase Correct 0 0 CTC 0 1 (Reserved Fast PWM 1 1 Fast PWM ICNC1 ICES1 – R/W R ATA6602/ATA6603 Update of TOP OCR1 0xFFFF Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP OCR1A Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP ICR1 BOTTOM OCR1A BOTTOM ICR1 ...
Page 156
... COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. ATA6602/ATA6603 156 and Figure 4-50 on page ...
Page 157
... TCNT1[15:8] TCNT1[7:0] R/W R/W R/W R 133 OCR1A[15:8] OCR1A[7:0] R/W R/W R/W R OCR1B[15:8] OCR1B[7:0] R/W R/W R/W R “Accessing 16-bit Registers” on page ATA6602/ATA6603 R/W R/W R/W R “Accessing 16-bit R/W R/W R/W R R/W R/W R/W R 133). TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ...
Page 158
... Initial Value • Bit 7, 6 – Res: Reserved Bits These bits are unused bits in the ATA6602/ATA6603, and will always read as zero. • Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled ...
Page 159
... Initial Value • Bit 7, 6 – Res: Reserved Bits These bits are unused bits in the ATA6602/ATA6603, and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Reg- ister (ICR1) is set by the WGM13 used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value ...
Page 160
... I/O Register and bit locations are listed in the page 172. The PRTIM2 bit in enable Timer/Counter2 module. Figure 4-53. 8-bit Timer/Counter Block Diagram Timer/Counter TCNTn = OCRnA = OCRnB TCCRnA ATA6602/ATA6603 160 “Power Reduction Register - PRR” on page 64 Count Clear Control Logic clk Direction TN Prescaler TOP BOTTOM = ...
Page 161
... OCR2A Register. The assignment is dependent on the mode of operation default equal to the MCU clock, clk T2 179). For details on clock sources and prescaler, 181. ATA6602/ATA6603 for details. The compare match event will also . When the AS2 I/O “Asyn- 161 ...
Page 162
... For more details about advanced counting sequences and waveform generation (see Operation” on page The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by the WGM22:0 bits. TOV2 can be used for generating a CPU interrupt. ATA6602/ATA6603 162 DATA BUS count clear ...
Page 163
... COM2x1:0 bits settings define whether the OC2x pin is set, cleared or toggled). 4921E–AUTO–09/09 shows a block diagram of the Output Compare unit. DATA BUS OCRnx = (8-bit Comparator) top bottom Waveform Generator FOCn WGMn1:0 ATA6602/ATA6603 “Modes of Operation” on page TCNTn OCFnx (Int.Req.) OCnx COMnX1:0 163 ...
Page 164
... I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM2x1:0 bits are shown. When referring to the OC2x state, the reference is for the internal OC2x Register, not the OC2x pin. ATA6602/ATA6603 164 Figure 4-56 on page 165 shows a 4921E– ...
Page 165
... For non-PWM modes, the action can be forced to have immediate effect by using the FOC2x strobe bits. 4921E–AUTO–09/09 COMnx1 Waveform COMnx0 Generator FOCnx clk I/O “8-bit Timer/Counter Register Description” on page Table 4-61 on page ATA6602/ATA6603 OCnx PORT D Q DDR 172). ...
Page 166
... The timing diagram for the CTC mode is shown in increases until a compare match occurs between TCNT2 and OCR2A, and then counter (TCNT2) is cleared. Figure 4-57. CTC Mode, Timing Diagram ATA6602/ATA6603 166 “Compare Match Output Unit” on page “Timer/Counter Timing Diagrams” on page ...
Page 167
... PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x and TCNT2. 4921E–AUTO–09/09 f clk_I/O ------------------------------------------------------ - N OCRnx TOV2 Figure 4-58 on page ATA6602/ATA6603 Flag is set in the same timer clock cycle that the 168. The TCNT2 value is in the timing diagram = OC2A 167 ...
Page 168
... OC2x to toggle its logical level on each compare match (COM2x1:0 = 1). The waveform generated will have a maximum frequency of f ture is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. ATA6602/ATA6603 168 1 2 ...
Page 169
... The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. 4921E–AUTO–09/09 4-59. The TCNT2 value is in the timing diagram shown as a histogram for illustrating 1 ATA6602/ATA6603 OCnx Interrupt OCRnx Update TOVn Interrupt (COMnx1 (COMnx1 ...
Page 170
... Figure 4-60 count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 4-60. Timer/Counter Timing Diagram, no Prescaling clk (clk I/O TCNTn TOVn ATA6602/ATA6603 170 f clk_I/O = -------------------- - N 510 Figure 4-59 on page 169 contains timing data for basic Timer/Counter operation. The figure shows the ...
Page 171
... I/O clk Tn /8) I/O OCRnx - 1 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. caler (f /8) clk_I/O clk I/O clkTN /8) I/O TOP - 1 ATA6602/ATA6603 /8) clk_I/O MAX BOTTOM OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP BOTTOM + 1 /8) clk_I/O OCRnx + 2 BOTTOM + 1 171 ...
Page 172
... CTC mode (non-PWM). Table 4-58. COM2A1 Table 4-59 mode. Table 4-59. COM2A1 Note: ATA6602/ATA6603 172 COM2A1 COM2A0 COM2B1 COM2B0 R/W R/W R Table 4-58 shows the COM2A1:0 bit functionality when the WGM22:0 Compare Output Mode, non-PWM Mode COM2A0 ...
Page 173
... A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at TOP. See page 169 for more details. ATA6602/ATA6603 (1) “Phase Correct PWM Mode” on (1) “Phase Correct PWM Mode” on ...
Page 174
... Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the ATA6602/ATA6603 and will always read as zero. • Bits 1:0 – WGM21:0: Waveform Generation Mode Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting ...
Page 175
... OCR2B as TOP. The FOC2B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATA6602/ATA6603 and will always read as zero. • Bit 3 – WGM22: Waveform Generation Mode See the description in • Bit 2:0 – CS22:0: Clock Select ...
Page 176
... Bit Read/Write Initial Value The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt generate a waveform output on the OC2B pin. ATA6602/ATA6603 176 Clock Select Bit Description CS21 CS20 Description ...
Page 177
... Interrupt Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed. 4921E–AUTO–09/ – – – – – – – – ATA6602/ATA6603 – OCIE2B OCIE2A TOIE2 R R/W R/W R – OCF2B OCF2A TOV2 R R/W R/W R TIMSK2 TIFR2 177 ...
Page 178
... TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the user is in doubt whether the time before re-entering Power-save or ADC Noise Reduction mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed: ATA6602/ATA6603 178 TCR2xUB. Enable interrupts, if needed. ...
Page 179
... Note that the crystal Oscillator will only run when this bit is zero. 4921E–AUTO–09/09 ) again becomes active, TCNT2 will read as the previous value (before entering I – EXCLK AS2 TCN2UB OCR2AUB R R/W R ATA6602/ATA6603 OCR2BUB TCR2AUB TCR2BUB ASSR R 0 179 ...
Page 180
... The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are differ- ent. When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A and TCCR2B the value in the temporary storage register is read. ATA6602/ATA6603 180 4921E–AUTO–09/09 ...
Page 181
... By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously IO /256, and clk /1024. Additionally, clk T2S T2S TSM – – – R ATA6602/ATA6603 10-BIT T/C PRESCALER 0 clk T2 . clk is by default connected to the main T2S T2S /8, clk /32, clk T2S T2S as well as 0 (stop) may be selected. T2S – – PSRASY PSRSYNC GTCCR ...
Page 182
... Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATA6602/ATA6603 and peripheral devices or between several AVR devices. The ATA6602/ATA6603 SPI includes the following features: • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • ...
Page 183
... SPI Data Register before the next character has been completely shifted in. Oth- erwise, the first byte is lost. 4921E–AUTO–09/09 LSB MASTER MSB 8 BIT SHIFT REGISTER SPI CLOCK GENERATOR ATA6602/ATA6603 Figure MSB SLAVE MISO MISO 8 BIT SHIFT REGISTER MOSI MOSI SHIFT ENABLE ...
Page 184
... Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. ATA6602/ATA6603 184 Table 4-66. For more details on automatic port overrides, refer to 93 ...
Page 185
... Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) } Note: 4921E–AUTO–09/09 (1) r17,(1<<DD_MOSI)|(1<<DD_SCK) DDR_SPI,r17 r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) SPCR,r17 SPDR,r16 ( The example code assumes that the part specific header file is included. ATA6602/ATA6603 185 ...
Page 186
... SPCR = (1<<SPE); } char SPI_SlaveReceive(void Wait for reception complete */ while(!(SPSR & (1<<SPIF))) /* Return Data Register */ return SPDR; } Note: ATA6602/ATA6603 186 (1) r17,(1<<DD_MISO) DDR_SPI,r17 r17,(1<<SPE) SPCR,r17 r16,SPDR ( The example code assumes that the part specific header file is included. ...
Page 187
... When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted first. 4921E–AUTO–09/ SPIE SPE DORD MSTR CPOL R/W R/W R/W R/W R ATA6602/ATA6603 CPHA SPR1 SPR0 SPCR R/W R/W R 187 ...
Page 188
... Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock fre- quency f Table 4-69. SPI2X ATA6602/ATA6603 188 Figure 4-67 and CPOL Functionality CPOL ...
Page 189
... SPI Data Register. • Bit 5..1 – Res: Reserved Bits These bits are reserved bits in the ATA6602/ATA6603 and will always read as zero. • Bit 0 – SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see period will be two CPU clock periods ...
Page 190
... CPOL=0, CPHA=0 CPOL=0, CPHA=1 CPOL=1, CPHA=0 CPOL=1, CPHA=1 Figure 4-67. SPI Transfer Format with CPHA = 0 Figure 4-68. SPI Transfer Format with CPHA = 1 ATA6602/ATA6603 190 Figure 4-68. Data bits are shifted out and latched in on opposite edges of the SCK sig- and Table 4-68, as done below ...
Page 191
... Overview A simplified block diagram of the USART Transmitter is shown in accessible I/O Registers and I/O pins are shown in bold. 4921E–AUTO–09/09 ATA6602/ATA6603 “USART in SPI Mode” on page “Power Reduction Register - PRR” on page 64 Figure 4-69 on page 218. The 192. CPU ...
Page 192
... The recovery units are used for asynchronous data reception. In addition to the recovery units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and can detect Frame Error, Data OverRun and Parity Errors. ATA6602/ATA6603 192 (1) UBRRn [H:L] ...
Page 193
... DDR_XCKn UCPOLn Transmitter clock (Internal Signal). Receiver base clock (Internal Signal). Input from XCK pin (internal Signal). Used for synchronous slave operation. Clock output to XCK pin (Internal Signal). Used for synchronous master operation. XTAL pin frequency (System Clock). ATA6602/ATA6603 U2Xn / DDR_XCKn 0 ...
Page 194
... For the Transmitter, there are no downsides. ATA6602/ATA6603 194 contains equations for calculating the baud rate (in bits per second) and for calculat- ...
Page 195
... Figure 4-70 on page 193 f OSC ---------- - 4 depends on the stability of the system clock source therefore recommended to osc UCPOL = 1 XCK RxD / TxD UCPOL = 0 XCK RxD / TxD Figure 4-71 shows, when UCPOLn is zero the data will be changed at ATA6602/ATA6603 for details. Sample Sample 195 ...
Page 196
... USART Stop Bit Select (USBSn) bit. The Receiver ignores the second stop bit (Frame Error) will therefore only be detected in the cases where the first stop bit is zero. ATA6602/ATA6603 196 illustrates the possible combinations of the frame formats. Bits inside brackets are ...
Page 197
... For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers. 4921E–AUTO–09/ even n 1 – odd n 1 – Parity bit using even parity even odd Parity bit using odd parity Data bit n of the character n ATA6602/ATA6603 197 ...
Page 198
... However, many applications use a fixed setting of the baud and control registers, and for these types of applications the initialization code can be placed directly in the main routine combined with initialization code for other I/O modules. ATA6602/ATA6603 198 (1) UBRRnH, r17 UBRRnL, r16 r16, (1< ...
Page 199
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATA6602/ATA6603 199 ...
Page 200
... Put data into buffer, sends the data */ UDRn = data; } Notes: The ninth bit can be used for indicating an address frame when using multi processor communi- cation mode or for other protocol handling as for example synchronization. ATA6602/ATA6603 200 (1)(2) UCSRnB,TXB8 UCSRnB,TXB8 UDRn,r16 (1)(2) ...