ATA6603-EK Atmel, ATA6603-EK Datasheet - Page 322

• Manufacturer Part Number: ATA6603-EK
• Description: MCU, MPU & DSP Development Tools Demoboard LIN-MCM
• Manufacturer: Atmel

Specifications of ATA6603-EK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.26.2.1
5. 2-wire Serial Interface Characteristics
Table 5-1
Interface meets or exceeds these requirements under the noted conditions.
Timing symbols refer to
Table 5-1.
322
Symbol
Notes:
Vhys
VOL
tSP
tof
VIH
VIL
tr
I
(1)
i
(1)
(1)
(1)
(1)
1. In ATA6602/ATA6603, this parameter is characterized and not 100% tested.
2. Required only for f
3. C
4. f
5. This requirement applies to all ATA6602/ATA6603 2-wire Serial Interface operation. Other devices connected to the 2-wire
6. The actual low period generated by the ATA6602/ATA6603 2-wire Serial Interface is (1/f
7. The actual low period generated by the ATA6602/ATA6603 2-wire Serial Interface is (1/f
ATA6602/ATA6603
describes the requirements for devices connected to the 2-wire Serial Bus. The ATA6602/ATA6603 2-wire Serial
Parameter
Input Low-voltage
Input High-voltage
Hysteresis of Schmitt Trigger Inputs
Output Low-voltage
Rise Time for both SDA and SCL
Output Fall Time from V
Spikes Suppressed by Input Filter
Input Current each I/O Pin
Serial Bus need only obey the general f
greater than 6 MHz for the low time requirement to be strictly met at f
requirement will not be strictly met for f
bus may communicate at full speed (400 kHz) with other ATA6602/ATA6603 devices, as well as any other device with a
proper t
CK
RC Oscillator Precision for LIN Slave implementation
b
2-wire Serial Bus Requirements
= capacitance of one bus line in pF.
= CPU clock frequency
LOW
acceptance margin.
Figure 5-1 on page
For LIN slave devices, the precision of the RC oscillator before and after re-synchronization are
described in the
Table 4-130. Oscillator Tolerance Before and After Re-synchronization Algorithm
Parameter
F
F
TOL_UNSYNCH
TOL_SYNCH
SCL
> 100 kHz.
IHmin
to V
ILmax
(2.7V < V
Table
324.
Clock Tolerance
Deviation of slave node clock from the nominal clock rate before
synchronization; relevant for nodes making use of
synchronization and direct SYNCH BREAK detection.
Deviation of slave node clock relative to the master node clock
after synchronization; relevant for nodes making use of
synchronization; any slave node must stay within this tolerance
for all fields of a frame which follow the SYNCH FIELD.
Note:
SCL
SCL
4-130.
> 308 kHz when f
CC
requirement.
Condition
10 pF < C
0.1V
3 mA sink current
< 5.5V, -40 C to +125 C)
For communication between any two nodes their bit
rate must not differ by more than ±2%.
CC
< V
b
i
< 400 pF
< 0.9V
CK
= 8 MHz. Still, ATA6602/ATA6603 devices connected to the
CC
(3)
SCL
= 100 kHz.
20 + 0.1C
20 + 0.1C
0.05 V
0.7 V
Min
-0.5
-10
0
0
SCL
SCL
CC
CC
b
b
(2)
(2,3)
(2,3)
- 2/f
- 2/f
CK
CK
), thus f
), thus the low time
V
0.3 V
CC
Max
50
300
250
0.4
10
–
+ 0.5
±14.0%
±2.0%
(2)
CK
F/F
CC
4921E–AUTO–09/09
must be
Master
Units
µA
ns
ns
ns
V
V
V
V