ATA6603-EK Atmel, ATA6603-EK Datasheet - Page 239

• Manufacturer Part Number: ATA6603-EK
• Description: MCU, MPU & DSP Development Tools Demoboard LIN-MCM
• Manufacturer: Atmel

Specifications of ATA6603-EK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.19.6.5
4.19.6.6
4921E–AUTO–09/09
TWI (Slave) Address Register – TWAR
TWI (Slave) Address Mask Register – TWAMR
The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of
TWAR) to which the TWI will respond when programmed as a Slave Transmitter or Receiver,
and not needed in the Master modes. In multi master systems, TWAR must be set in masters
which can be addressed as Slaves by other Masters.
The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an
associated address comparator that looks for the slave address (or general call address if
enabled) in the received serial address. If a match is found, an interrupt request is generated.
Figure 4-86. TWI Address Match Logic, Block Diagram
• Bits 7..1 – TWA: TWI (Slave) Address Register
• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit
• Bits 7..1 – TWAM: TWI Address Mask
• Bit 0 – Res: Reserved Bit
Initial Value
Initial Value
Read/Write
Read/Write
These seven bits constitute the slave address of the TWI unit.
If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus.
The TWAMR can be loaded with a 7-bit Salve Address mask. Each of the bits in TWAMR
can mask (disable) the corresponding address bits in the TWI Address Register (TWAR). If
the mask bit is set to one then the address match logic ignores the compare between the
incoming address bit and the corresponding bit in TWAR.
match logic in detail.
This bit is an unused bit in the ATA6602/ATA6603, and will always read as zero.
Bit
Bit
TWA6
R/W
R/W
7
1
7
0
TWAMR0
Address
TWAR0
Bit 0
TWA5
R/W
R/W
6
1
6
0
Address Bit Comparator 6..1
TWA4
R/W
R/W
5
1
5
0
Address Bit Comparator 0
TWAM[6:0]
TWA3
R/W
R/W
4
1
4
0
TWA2
R/W
R/W
3
1
3
0
ATA6602/ATA6603
TWA1
R/W
R/W
2
1
2
0
Figure 4-86
TWA0
R/W
R/W
1
1
1
0
Address
Match
shown the address
TWGCE
R/W
R
0
0
0
–
0
TWAMR
TWAR
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