ATA6603-EK Atmel, ATA6603-EK Datasheet - Page 149

• Manufacturer Part Number: ATA6603-EK
• Description: MCU, MPU & DSP Development Tools Demoboard LIN-MCM
• Manufacturer: Atmel

Specifications of ATA6603-EK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.14.8.5
4921E–AUTO–09/09
Phase and Frequency Correct PWM Mode
The PWM frequency for the output when using phase correct PWM can be calculated by the fol-
lowing equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If
OCR1A is used to define the TOP value (WGM13:0 = 11) and COM1A1:0 = 1, the OC1A output
will toggle with a 50% duty cycle.
The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM
mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency correct PWM wave-
form generation option. The phase and frequency correct PWM mode is, like the phase correct
PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM
(0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the
Output Compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x while
upcounting, and set on the compare match while downcounting. In inverting Compare Output
mode, the operation is inverted. The dual-slope operation gives a lower maximum operation fre-
quency compared to the single-slope operation. However, due to the symmetric feature of the
dual-slope PWM modes, these modes are preferred for motor control applications.
The main difference between the phase correct, and the phase and frequency correct PWM
mode is the time the OCR1x Register is updated by the OCR1x Buffer Register (see
on page 148
The PWM resolution for the phase and frequency correct PWM mode can be defined by either
ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and
the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can
be calculated using the following equation:
In phase and frequency correct PWM mode the counter is incremented until the counter value
matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The
counter has then reached the TOP and changes the count direction. The TCNT1 value will be
equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency
correct PWM mode is shown on
quency correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in
the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram
includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1
slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will
be set when a compare match occurs.
f
R
OCnxPCPWM
PFCPWM
=
and
log
---------------------------------- -
=
---------------------------------
2
log
Figure 4-48 on page
TOP
f
clk_I/O
N
2
+
TOP
1
Figure 4-48 on page
150).
150. The figure shows phase and fre-
ATA6602/ATA6603
Figure 4-47
149