ATA6603-EK Atmel, ATA6603-EK Datasheet - Page 212

• Manufacturer Part Number: ATA6603-EK
• Description: MCU, MPU & DSP Development Tools Demoboard LIN-MCM
• Manufacturer: Atmel

Specifications of ATA6603-EK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.17.9.3
212
ATA6602/ATA6603
USART Control and Status Register n B – UCSRnB
Initial Value
• Bit 2 – UPEn: USART Parity Error
• Bit 1 – U2Xn: Double the USART Transmission Speed
• Bit 0 – MPCMn: Multi-processor Communication Mode
Read/Write
• Bit 7 – RXCIEn: RX Complete Interrupt Enable n
• Bit 6 – TXCIEn: TX Complete Interrupt Enable n
• Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable n
• Bit 4 – RXENn: Receiver Enable n
• Bit 3 – TXENn: Transmitter Enable n
This bit is set if the next character in the receive buffer had a Parity Error when received and
the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive
buffer (UDRn) is read. Always set this bit to zero when writing to UCSRnA.
This bit only has effect for the asynchronous operation. Write this bit to zero when using syn-
chronous operation.
Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively
doubling the transfer rate for asynchronous communication.
This bit enables the Multi-processor Communication mode. When the MPCMn bit is written
to one, all the incoming frames received by the USART Receiver that do not contain address
information will be ignored. The Transmitter is unaffected by the MPCMn setting. For more
detailed information see
Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete
interrupt will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in
SREG is written to one and the RXCn bit in UCSRnA is set.
Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete
interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in
SREG is written to one and the TXCn bit in UCSRnA is set.
Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt
will be generated only if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG
is written to one and the UDREn bit in UCSRnA is set.
Writing this bit to one enables the USART Receiver. The Receiver will override normal port
operation for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer
invalidating the FEn, DORn, and UPEn Flags.
Writing this bit to one enables the USART Transmitter. The Transmitter will override normal
port operation for the TxDn pin when enabled. The disabling of the Transmitter (writing
TXENn to zero) will not become effective until ongoing and pending transmissions are com-
pleted, i.e., when the Transmit Shift Register and Transmit Buffer Register do not contain
data to be transmitted. When disabled, the Transmitter will no longer override the TxDn port.
Bit
RXCIEn
R/W
7
0
TXCIEn
R/W
6
0
“Multi-processor Communication Mode” on page
UDRIEn
R/W
5
0
RXENn
R/W
4
0
TXENn
R/W
3
0
UCSZn2
R/W
2
0
RXB8n
R
1
0
209.
TXB8n
R/W
0
0
4921E–AUTO–09/09
UCSRnB