ATA6603P-PLQW Atmel, ATA6603P-PLQW Datasheet - Page 158

• Manufacturer Part Number: ATA6603P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6603P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.14.10.7
4.14.10.8
158
ATA6602/ATA6603
Input Capture Register 1 – ICR1H and ICR1L
Timer/Counter1 Interrupt Mask Register – TIMSK1
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the
ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers (see
Bit
Read/Write
Initial Value
• Bit 7, 6 – Res: Reserved Bits
• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
• Bit 4, 3 – Res: Reserved Bits
• Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
• Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
Read/Write
Initial Value
These bits are unused bits in the ATA6602/ATA6603, and will always read as zero.
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Inter-
rupt Vector (see
is set.
These bits are unused bits in the ATA6602/ATA6603, and will always read as zero.
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corre-
sponding Interrupt Vector (see
located in TIFR1, is set.
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corre-
sponding Interrupt Vector (see
located in TIFR1, is set.
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt
Vector (see
TIFR1, is set.
Bit
“Accessing 16-bit Registers” on page
R/W
“Watchdog Timer” on page
R
7
–
0
7
0
“Interrupts” on page
R/W
R
6
–
0
6
0
ICIE1
R/W
R/W
5
0
“Interrupts” on page
“Interrupts” on page
5
0
77) is executed when the ICF1 Flag, located in TIFR1,
R/W
R
4
–
0
4
0
ICR1[15:8]
72) is executed when the TOV1 Flag, located in
ICR1[7:0]
133).
R/W
R
3
–
0
3
0
77) is executed when the OCF1B Flag,
77) is executed when the OCF1A Flag,
OCIE1B
R/W
R/W
2
0
2
0
OCIE1A
R/W
R/W
1
0
1
0
TOIE1
R/W
R/W
0
0
0
0
4921E–AUTO–09/09
TIMSK1
ICR1H
ICR1L