ATA6603P-PLQW Atmel, ATA6603P-PLQW Datasheet - Page 350

• Manufacturer Part Number: ATA6603P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6603P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.5
350
BIT AND BIT-TEST INSTRUCTIONS
Note:
Mnemonics
SWAP
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRGE
BRHS
BRHC
SBRS
BRBS
BRLO
BRPL
BRTS
BRTC
BRVS
BRVC
BSET
BCLR
BRMI
BRLT
SBIC
BRIE
BRID
SBIS
ROR
ROL
ASR
SEC
CLC
SEN
CLN
LSR
BST
BLD
SEZ
CLZ
LSL
SBI
CBI
SEI
Instruction Set Summary (Continued)
1. These instructions are only available in ATA6603
ATA6602/ATA6603
Operands
Rd, b
Rr, b
Rr, b
P, b
P, b
s, k
s, k
P,b
P,b
Rd
Rd
Rd
Rd
Rd
Rd
s
s
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
Description
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Branch if Not Equal
Branch if Carry Set
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
Branch if Minus
Branch if Plus
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
Logical Shift Right
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Flag Set
Flag Clear
Bit Store from Register to T
Bit load from T to Register
Set Carry
Clear Carry
Set Negative Flag
Clear Negative Flag
Set Zero Flag
Clear Zero Flag
Global Interrupt Enable
Operation
if (Rr(b)=1) PC
if (P(b)=0) PC
if (P(b)=1) PC
if (SREG(s) = 1) then PC PC+k + 1
if (SREG(s) = 0) then PC PC+k + 1
if (Z = 1) then PC
if (Z = 0) then PC
if (C = 1) then PC
if (C = 0) then PC
if (C = 0) then PC
if (C = 1) then PC
if (N = 1) then PC
if (N = 0) then PC
if (N
if (N
if (H = 1) then PC
if (H = 0) then PC
if (T = 1) then PC
if (T = 0) then PC
if (V = 1) then PC
if (V = 0) then PC
if ( I = 1) then PC
if ( I = 0) then PC
I/O(P,b)
I/O(P,b)
Rd(n+1)
Rd(n)
Rd(0) C,Rd(n+1) Rd(n),C Rd(7)
Rd(7) C,Rd(n) Rd(n+1),C Rd(0)
Rd(n)
Rd(3..0) Rd(7..4),Rd(7..4) Rd(3..0)
SREG(s)
SREG(s)
T
Rd(b)
C
C
N
N
Z
Z
I
1
Rr(b)
1
0
1
0
1
0
V= 0) then PC
V= 1) then PC
Rd(n+1), Rd(7)
Rd(n+1), n=0..6
T
1
0
Rd(n), Rd(0)
1
0
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
0
0
SREG(s)
SREG(s)
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Flags
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
T
C
C
N
N
Z
Z
I
4921E–AUTO–09/09
#Clocks
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1