ATA6613P-PLQW Atmel, ATA6613P-PLQW Datasheet - Page 226

• Manufacturer Part Number: ATA6613P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.18.6
6.18.6.1
6.18.6.2
226
Atmel ATA6612/ATA6613
USART MSPIM Register Description
USART MSPIM I/O Data Register - UDRn
USART MSPIM Control and Status Register n A - UCSRnA
The following section describes the registers used for SPI operation using the USART.
The function and bit description of the USART data register (UDRn) in MSPI mode is identical
to normal USART operation (see
Read/Write
Initial Value
• Bit 7 - RXCn: USART Receive Complete
• Bit 6 - TXCn: USART Transmit Complete
• Bit 5 - UDREn: USART Data Register Empty
• Bit 4:0 - Reserved Bits in MSPI mode
This flag bit is set when there are unread data in the receive buffer and cleared when the
receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled,
the receive buffer will be flushed and consequently the RXCn bit will become zero. The
RXCn Flag can be used to generate a Receive Complete interrupt (see description of the
RXCIEn bit).
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted
out and there are no new data currently present in the transmit buffer (UDRn). The TXCn
Flag bit is automatically cleared when a transmit complete interrupt is executed, or it can
be cleared by writing a one to its bit location. The TXCn Flag can generate a Transmit
Complete interrupt (see description of the TXCIEn bit).
The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If
UDREn is one, the buffer is empty, and therefore ready to be written. The UDREn Flag
can generate a Data Register Empty interrupt (see description of the UDRIE bit). UDREn
is set after a reset to indicate that the Transmitter is ready.
When in MSPI mode, these bits are reserved for future use. For compatibility with future
devices, these bits must be written to zero when UCSRnA is written.
Bit
RXCn
R/W
7
0
TXCn
R/W
6
0
UDREn
R/W
5
0
“USART I/O Data Register n– UDRn” on page
R
4
0
-
R
3
0
-
R
2
1
-
R
1
1
-
R
0
0
-
9111H–AUTO–01/11
212).
UCSRnA