PIC18LF4455-I/PT Microchip Technology, PIC18LF4455-I/PT Datasheet - Page 180

• Manufacturer Part Number: PIC18LF4455-I/PT
• Description: IC PIC MCU FLASH 12KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF4455-I/PT

• Core Size: 8-Bit
• Program Memory Size: 24KB (12K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 2048Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, I2C, EAUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163025
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F2455/2550/4455/4550
17.4.4
An endpoint is defined to have a ping-pong buffer when
it has two sets of BD entries: one set for an Even
transfer and one set for an Odd transfer. This allows the
CPU to process one BD while the SIE is processing the
other BD. Double-buffering BDs in this way allows for
maximum throughput to/from the USB.
The USB module supports four modes of operation:
• No ping-pong support
• Ping-pong buffer support for OUT Endpoint 0 only
• Ping-pong buffer support for all endpoints
• Ping-pong buffer support for all other Endpoints
The ping-pong buffer settings are configured using the
PPB1:PPB0 bits in the UCFG register.
The USB module keeps track of the Ping-Pong Pointer
individually for each endpoint. All pointers are initially
reset to the Even BD when the module is enabled. After
FIGURE 17-7:
DS39632E-page 178
400h
47Fh
4FFh
except Endpoint 0
Note:
Maximum Memory
Used: 128 bytes
Maximum BDs:
32 (BD0 to BD31)
PPB1:PPB0 = 00
No Ping-Pong
Data RAM
Available
Buffers
as
PING-PONG BUFFERING
Memory area not shown to scale.
EP0 OUT
Descriptor
EP0 IN
Descriptor
EP1 OUT
Descriptor
EP1 IN
Descriptor
EP15 IN
Descriptor
BUFFER DESCRIPTOR TABLE MAPPING FOR BUFFERING MODES
400h
483h
4FFh
Ping-Pong Buffer
PPB1:PPB0 = 01
Maximum Memory
Used: 132 bytes
Maximum BDs:
33 (BD0 to BD32)
on EP0 OUT
Data RAM
Available
as
EP0 OUT Even
Descriptor
EP0 OUT Odd
Descriptor
EP0 IN
Descriptor
EP1 OUT
Descriptor
EP1 IN
Descriptor
EP15 IN
Descriptor
4FFh
400h
Ping-Pong Buffers
Maximum Memory
Used: 256 bytes
Maximum BDs:
64 (BD0 to BD63)
PPB1:PPB0 = 10
on all EPs
the completion of a transaction (UOWN cleared by the
SIE), the pointer is toggled to the Odd BD. After the
completion of the next transaction, the pointer is
toggled back to the Even BD and so on.
The Even/Odd status of the last transaction is stored in
the PPBI bit of the USTAT register. The user can reset
all Ping-Pong Pointers to Even using the PPBRST bit.
Figure 17-7 shows the four different modes of
operation and how USB RAM is filled with the BDs.
BDs have a fixed relationship to a particular endpoint,
depending on the buffering configuration. The mapping
of BDs to endpoints is detailed in Table 17-4. This
relationship also means that gaps may occur in the
BDT if endpoints are not enabled contiguously. This
theoretically means that the BDs for disabled endpoints
could be used as buffer space. In practice, users
should avoid using such spaces in the BDT unless a
method of validating BD addresses is implemented.
EP0 OUT Even
Descriptor
EP0 OUT Odd
Descriptor
EP0 IN Even
Descriptor
EP0 IN Odd
Descriptor
EP1 OUT Even
Descriptor
EP1 OUT Odd
Descriptor
EP1 IN Odd
Descriptor
EP15 IN Odd
Descriptor
EP1 IN Even
Descriptor
4F7h
4FFh
400h
© 2009 Microchip Technology Inc.
Ping-Pong Buffers
Maximum Memory
Used: 248 bytes
Maximum BDs:
62 (BD0 to BD61)
PPB1:PPB0 = 11
on all other EPs
Data RAM
Available
except EP0
as
EP0 OUT
Descriptor
EP0 IN
Descriptor
EP1 OUT Even
Descriptor
EP1 OUT Odd
Descriptor
EP1 IN Odd
Descriptor
EP15 IN Odd
Descriptor
EP1 IN Even
Descriptor