PIC18LF4455-I/PT Microchip Technology, PIC18LF4455-I/PT Datasheet - Page 434

• Manufacturer Part Number: PIC18LF4455-I/PT
• Description: IC PIC MCU FLASH 12KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF4455-I/PT

• Core Size: 8-Bit
• Program Memory Size: 24KB (12K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 2048Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, I2C, EAUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163025
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F2455/2550/4455/4550
Timing Diagrams and Specifications ................................ 387
Top-of-Stack Access .......................................................... 60
TQFP Packages and Special Features ............................ 311
TSTFSZ ............................................................................ 353
Two-Speed Start-up ................................................. 291, 305
Two-Word Instructions
TXSTA Register
U
Universal Serial Bus ........................................................... 65
DS39632E-page 432
Transition for Two-Speed Start-up
Transition for Wake From Idle to Run Mode .............. 41
Transition for Wake from Sleep (HSPLL) ................... 40
Transition From RC_RUN Mode to
Transition from SEC_RUN Mode to
Transition to RC_RUN Mode ..................................... 39
USB Signal ............................................................... 402
Capture/Compare/PWM Requirements
CLKO and I/O Requirements ................................... 389
EUSART Synchronous Receive
EUSART Synchronous Transmission
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
External Clock Requirements .................................. 387
I
I
Master SSP I
Master SSP I
PLL Clock ................................................................. 388
Reset, Watchdog Timer, Oscillator Start-up
Streaming Parallel Port Requirements
Timer0 and Timer1 External Clock
USB Full-Speed Requirements ................................ 402
USB Low-Speed Requirements ............................... 402
Example Cases .......................................................... 64
BRGH Bit ................................................................. 247
Address Register (UADDR) ..................................... 173
and Streaming Parallel Port ..................................... 187
Associated Registers ............................................... 187
Buffer Descriptor Table ............................................ 174
2
2
C Bus Data Requirements (Slave Mode) .............. 398
C Bus Start/Stop Bits Requirements ..................... 397
(INTOSC to HSPLL) ......................................... 305
PRI_RUN Mode ................................................. 39
PRI_RUN Mode (HSPLL) .................................. 37
(All CCP Modules) ........................................... 392
Requirements ................................................... 401
Requirements ................................................... 401
(Master Mode, CKE = 0) .................................. 393
(Master Mode, CKE = 1) .................................. 394
(Slave Mode, CKE = 0) .................................... 395
(Slave Mode, CKE = 1) .................................... 396
Requirements ................................................... 399
Timer, Power-up Timer and
Brown-out Reset Requirements ....................... 390
(PIC18F4455/4550) ......................................... 403
Requirements ................................................... 391
2
2
C Bus Data Requirements ................ 400
C Bus Start/Stop Bits
USB. See Universal Serial Bus.
V
Voltage Reference Specifications .................................... 382
W
Watchdog Timer (WDT) ........................................... 291, 303
WCOL ...................................................... 230, 231, 232, 235
WCOL Status Flag ................................... 230, 231, 232, 235
WWW Address ................................................................ 433
WWW, On-Line Support ...................................................... 5
X
XORLW ............................................................................ 353
XORWF ........................................................................... 354
Buffer Descriptors .................................................... 174
Class Specifications and Drivers ............................. 190
Descriptors ............................................................... 190
Endpoint Control ...................................................... 172
Enumeration ............................................................ 190
External Pull-up Resistors ....................................... 169
External Transceiver ................................................ 167
Eye Pattern Test Enable .......................................... 169
Firmware and Drivers .............................................. 187
Frame Number Registers ........................................ 173
Frames .................................................................... 189
Internal Pull-up Resistors ......................................... 169
Internal Transceiver ................................................. 167
Internal Voltage Regulator ....................................... 170
Interrupts ................................................................. 180
Layered Framework ................................................. 189
Oscillator Requirements .......................................... 187
Output Enable Monitor ............................................. 169
Overview .......................................................... 165, 189
Ping-Pong Buffer Configuration ............................... 169
Power ...................................................................... 189
Power Modes ........................................................... 186
RAM ......................................................................... 173
Speed ...................................................................... 190
Status and Control ................................................... 166
Transfer Types ......................................................... 189
UFRMH:UFRML Registers ...................................... 173
Associated Registers ............................................... 304
Control Register ....................................................... 303
During Oscillator Failure .......................................... 306
Programming Considerations .................................. 303
Address Validation ........................................... 177
Assignment in Different Buffering Modes ........ 179
BDnSTAT Register (CPU Mode) ..................... 175
BDnSTAT Register (SIE Mode) ....................... 177
Byte Count ....................................................... 177
Example ........................................................... 174
Memory Map .................................................... 178
Ownership ....................................................... 174
Ping-Pong Buffering ........................................ 178
Register Summary ........................................... 179
Status and Configuration ................................. 174
and USB Transactions ..................................... 180
Bus Power Only ............................................... 186
Dual Power with Self-Power Dominance ......... 186
Self-Power Only ............................................... 186
Memory Map .................................................... 173
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