PIC18LF4455-I/PT Microchip Technology, PIC18LF4455-I/PT Datasheet - Page 204

• Manufacturer Part Number: PIC18LF4455-I/PT
• Description: IC PIC MCU FLASH 12KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF4455-I/PT

• Core Size: 8-Bit
• Program Memory Size: 24KB (12K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 2048Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, I2C, EAUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163025
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F2455/2550/4455/4550
19.3.5
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 19-2) is to
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be dis-
abled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
The clock polarity is selected by appropriately
programming the CKP bit (SSPCON1<4>). This, then,
would give waveforms for SPI communication as
shown in Figure 19-3, Figure 19-5 and Figure 19-6,
where the MSB is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user-programmable to be one
of the following:
EXAMPLE 19-2:
DS39632E-page 202
TransmitSPI:
BCF
MOVF
MOVWF
BCF
CLRF
MOVF
MOVWF
BSF
WaitComplete:
BTFSS
BRA
PIR1, SSPIF
SSPBUF, W
RXDATA
T2CON, TMR2ON
TMR2
TXDATA, W
SSPBUF
T2CON, TMR2ON
PIR1, SSPIF
WaitComplete
MASTER MODE
LOADING SSPBUF WITH THE TIMER2/2 CLOCK MODE
;Make sure interrupt flag is clear (may have been set from previous
transmission)
;Perform read, even if the data in SSPBUF is not important
;Save previously received byte in user RAM, if the data is meaningful
;Turn off timer when loading SSPBUF
;Set timer to a known state
;WREG = Contents of TXDATA (user data to send)
;Load data to send into transmit buffer
;Start timer to begin transmission
;Loop until data has finished transmitting
;Interrupt flag set when transmit is complete
• F
• F
• F
• Timer2 output/2
This allows a maximum data rate (at 48 MHz) of
12.00 Mbps.
When used in Timer2 Output/2 mode, the bit rate can
be configured using the PR2 Period register and the
Timer2 prescaler. However, writing to SSPBUF does
not clear the current TMR2 value in hardware. Depend-
ing upon the current value of TMR2 when the user firm-
ware writes to SSPBUF, this can result in an
unpredictable MSb bit width, unless the procedure of
Example 19-2 is used.
Figure 19-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
OSC
OSC
OSC
/4 (or T
/16 (or 4 • T
/64 (or 16 • T
CY
)
CY
CY
)
)
© 2009 Microchip Technology Inc.