AT32UC3A1128-AUT Atmel, AT32UC3A1128-AUT Datasheet - Page 101

• Manufacturer Part Number: AT32UC3A1128-AUT
• Description: IC MCU AVR32 128KB FLASH 100TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A1128-AUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Controller Family/series: AT32UC3A
• No. Of I/o's: 69
• Ram Memory Size: 32KB
• Cpu Speed: 66MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, RS-485, SPI, USART
• Maximum Clock Frequency: 66 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
• Minimum Operating Temperature: - 40 C
• Package: 100TQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16.4
16.4.1
16.4.2
32058J–AVR32–04/11
User Interface
Memory Map
Interrupt Request Map
pipeline stall, which prevents the interrupt from accidentally re-triggering in case the handler is
exited and the interrupt mask is cleared before the interrupt request is cleared.
This chapter lists the INTC registers are accessible through the PB bus. The registers are used
to control the behaviour and read the status of the INTC.
The following table shows the address map of the INTC registers, relative to the base address of
the INTC.
Table 16-1.
The mapping of interrupt requests from peripherals to INTREQs is presented in the Peripherals
Section.
Offset
0
4
...
252
256
260
...
508
512
516
520
524
Register
Interrupt Priority Register 0
Interrupt Priority Register 1
...
Interrupt Priority Register 63
Interrupt Request Register 0
Interrupt Request Register 1
...
Interrupt Request Register 63
Interrupt Cause Register 3
Interrupt Cause Register 2
Interrupt Cause Register 1
Interrupt Cause Register 0
INTC address map
Name
IPR0
IPR1
...
IPR63
IRR0
IRR1
...
IRR63
ICR3
ICR2
ICR1
ICR0
Access
Read/Write
Read/Write
...
Read/Write
Read-only
Read-only
...
Read-only
Read-only
Read-only
Read-only
Read-only
Reset Value
0x0000_0000
0x0000_0000
...
0x0000_0000
N/A
N/A
...
N/A
N/A
N/A
N/A
N/A
AT32UC3A
101