AT32UC3A1128-AUT Atmel, AT32UC3A1128-AUT Datasheet - Page 815

• Manufacturer Part Number: AT32UC3A1128-AUT
• Description: IC MCU AVR32 128KB FLASH 100TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A1128-AUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Controller Family/series: AT32UC3A
• No. Of I/o's: 69
• Ram Memory Size: 32KB
• Cpu Speed: 66MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, RS-485, SPI, USART
• Maximum Clock Frequency: 66 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
• Minimum Operating Temperature: - 40 C
• Package: 100TQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

41. 5 . 17
41.5.14
41.5.15
41.5.16
32058J–AVR32–04/11
F LASHC
OCD
PDCA
TWI
1. Reading from on-chip flash may fail after a flash fuse write operation (FLASHC LP,
2. The RTC CLKEN bit (bit number 16) of CTRL register is not available.
1. Stalled memory access instruction writeback fails if followed by a HW breakpoint.
1. Wrong PDCA behavior when using two PDCA channels with the same PID.
1. The TWI RXRDY flag in SR register is not reset when a software reset is performed.
UP, WGPB, EGPB, SSB, PGPFB, EAGPF commands).
After a flash fuse write operation (FLASHC LP, UP, WGPB, EGPB, SSB, PGPFB, EAGPF
commands), the following flash read access may return corrupted data. This erratum does
not affect write operations to regular flash memory.
Fix/Workaround
The flash fuse write operation (FLASHC LP, UP, WGPB, EGPB, SSB, PGPFB, EAGPF
commands) must be issued from internal RAM. After the write operation, perform a dummy
flash page write operation (FLASHC WP). Content and location of this page is not important
and filling the write buffer with all one (FFh) will leave the current flash content unchanged. It
is then safe to read and fetch code from the flash.
Fix/Workaround
Do not use the CLKEN bit of the RTC on Rev E.
Consider the following assembly code sequence:
A
B
If a hardware breakpoint is placed on instruction B, and instruction A is a memory access
instruction, register file updates from instruction A can be discarded.
Fix/Workaround
Do not place hardware breakpoints, use software breakpoints instead.
Alternatively, place a hardware breakpoint on the instruction before the memory
access instruction and then single step over the memory access instruction.
Workaround/fix
The same PID should not be assigned to more than one channel.
Fix/Workaround
After a Software Reset, the register TWI RHR must be read.
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