AT32UC3A1128-AUT Atmel, AT32UC3A1128-AUT Datasheet - Page 44

• Manufacturer Part Number: AT32UC3A1128-AUT
• Description: IC MCU AVR32 128KB FLASH 100TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A1128-AUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Controller Family/series: AT32UC3A
• No. Of I/o's: 69
• Ram Memory Size: 32KB
• Cpu Speed: 66MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, RS-485, SPI, USART
• Maximum Clock Frequency: 66 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
• Minimum Operating Temperature: - 40 C
• Package: 100TQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

12.4.3
12.5
12.6
32058J–AVR32–04/11
Nexus OCD AUX port connections
PDC handshake signals
SPIs
Each SPI can be connected to an internally divided clock:
Table 12-6.
If the OCD trace system is enabled, the trace system will take control over a number of pins, irre-
spectively of the PIO configuration. Two different OCD trace pin mappings are possible,
depending on the configuration of the OCD AXS register. For details, see the AVR32 UC Tech-
nical Reference Manual.
Table 12-7.
The PDC and the peripheral modules communicate through a set of handshake signals. The fol-
lowing table defines the valid settings for the Peripheral Identifier (PID) in the PDC Peripheral
Select Register (PSR).
Table 12-8.
SPI
0
1
Pin
EVTI_N
MDO[5]
MDO[4]
MDO[3]
MDO[2]
MDO[1]
MDO[0]
EVTO_N
MCKO
MSEO[1]
MSEO[0]
PID Value
0
1
2
3
SPI clock connections
Nexus OCD AUX port connections
PDC Handshake Signals
AXS=0
PB19
PB16
PB14
PB13
PB12
PB11
PB10
PB20
PB21
PB04
PB17
Peripheral module & direction
ADC
SSC - RX
USART0 - RX
USART1 - RX
Source
Internal
Name
CLK_DIV
AXS=1
PA08
PA27
PA26
PA25
PA24
PA23
PA22
PB20
PA21
PA07
PA28
Connection
PBA clock or
PBA clock / 32
AT32UC3A
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