AT32UC3A1128-AUT Atmel, AT32UC3A1128-AUT Datasheet - Page 594

• Manufacturer Part Number: AT32UC3A1128-AUT
• Description: IC MCU AVR32 128KB FLASH 100TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A1128-AUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Controller Family/series: AT32UC3A
• No. Of I/o's: 69
• Ram Memory Size: 32KB
• Cpu Speed: 66MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, RS-485, SPI, USART
• Maximum Clock Frequency: 66 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
• Minimum Operating Temperature: - 40 C
• Package: 100TQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

AT32UC3A
• EOT_IRQ_EN: End of USB Transfer Interrupt Enable
Set this bit to enable the end of usb OUT data transfer interrupt.
This interrupt is generated only if the BUFF_CLOSE_IN_EN bit is set.
Clear this bit to disable this interrupt.
• EOBUFF_IRQ_EN: End of Buffer Interrupt Enable
Set this bit to enable the end of buffer interrupt.
This interrupt is generated when the channel byte count reaches zero.
Clear this bit to disable this interrupt.
• DESC_LD_IRQ_EN: Descriptor Loaded Interrupt Enable
Set this bit to enable the Descripor Loaded interrupt.
This interrupt is generated when a Descriptor has been loaded from the system bus.
Clear this bit to disable this interrupt.
• BURST_LOCK_EN: Burst Lock Enable
Set this bit to lock the HSB data burst for maximum optimization of HSB busses bandwidth usage and maximization of fly-
by duration.
If clear, the DMA never locks HSB access.
• CH_BYTE_LENGTH: Channel Byte Length
This field determines the total number of bytes to be transferred for this buffer.
The maximum channel transfer size 64 kB is reached when this field is 0 (default value).
If the transfer size is unknown, the transfer end is controlled by the peripheral and this field should be set to 0.
This field can be written by software or descriptor loading only after the UDDMAX_STATUS.CH_EN bit has been cleared,
otherwise this field is ignored.
594
32058J–AVR32–04/11