AT32UC3A1128-AUT Atmel, AT32UC3A1128-AUT Datasheet - Page 270

• Manufacturer Part Number: AT32UC3A1128-AUT
• Description: IC MCU AVR32 128KB FLASH 100TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A1128-AUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Controller Family/series: AT32UC3A
• No. Of I/o's: 69
• Ram Memory Size: 32KB
• Cpu Speed: 66MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, RS-485, SPI, USART
• Maximum Clock Frequency: 66 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
• Minimum Operating Temperature: - 40 C
• Package: 100TQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

25.7.6
25.7.6.1
25.7.7
32058J-AVR32-04/11
Receive Compare Modes
Data Format
Compare Functions
Figure 25-12. Receive Compare Modes
Compare 0 can be one start event of the Receiver. In this case, the receiver compares at each
new sample the last FSLEN bits received at the FSLEN lower bit of the data contained in the
Compare 0 Register (RC0R). When this start event is selected, the user can program the
Receiver to start a new data transfer either by writing a new Compare 0, or by receiving continu-
ously until Compare 1 occurs. This selection is done with the bit (STOP) in RCMR.
The data framing format of both the transmitter and the receiver are programmable through the
Transmitter Frame Mode Register (TFMR) and the Receiver Frame Mode Register (RFMR). In
either case, the user can independently select:
Additionally, the transmitter can be used to transfer synchronization and select the level driven
on the TX_DATA pin while not in data transfer operation. This is done respectively by the Frame
Sync Data Enable (FSDEN) and by the Data Default Value (DATDEF) bits in TFMR.
• the event that starts the data transfer (START)
• the delay in number of bit periods between the start event and the first data bit (
• the length of the data (DATLEN)
• the number of data to be transferred for each start event (DATNB).
• the length of synchronization transferred for each start event (FSLEN)
• the bit sense: most or lowest significant bit first (MSBF).
RX_CLOCK
RX_DATA
(Input)
CMP0
(4 in This Example)
CMP1
Up to 16 Bits
FSLEN
CMP2
CMP3
Start
STTDLY
Ignored
B0
DATLEN
AT32UC3A
B1
B2
STTDLY
)
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