PIC32MX795F512L-80I/PF Microchip Technology, PIC32MX795F512L-80I/PF Datasheet

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... PIC32MX5XX/6XX/7XX  2009 Microchip Technology Inc. Data Sheet USB, CAN and Ethernet 32-bit Flash Microcontrollers Preliminary DS61156B ...

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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

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... CAN module: - 2.0B Active with DeviceNet™ addressing support - Dedicated DMA channels • 3 MHz to 25 MHz crystal oscillator  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Peripheral Features (Continued): • Internal 8 MHz and 32 kHz oscillators • Six UART modules with: - RS-232, RS-485 and LIN 1.2 support ® ...

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... PIC32MX675F512L 100 512 + 12 64 (1) 512 + 12 PIC32MX695F512L 100 128 (1) PIC32MX795F512L 100 512 + 12 128 Legend: PF TQFP MR = QFN Note 1: This device features 12 KB boot Flash memory. 2: CTS and RTS pins may not be available for all UART modules. Refer to the “Pin Diagrams” section for more information ...

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... AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/V -/CV -/CN3/RB1 REF REF PGED1/AN0/V +/CV +/PMA6/CN2/RB0 REF REF Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V externally. SS  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX PIC32MX575F256H 9 PIC32MX575F512H 10 11 ...

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... The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V externally. SS DS61156B-page 6 = Pins are tolerant SOSCO/T1CK/CN0/RC14 47 SOSCI/CN1/RC13 OC1/INT0/RD0 46 ECRS/AERXCLK/IC4/PMCS1/PMA14/INT4/RD11 45 44 ECOL/AERXDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 43 AERXD0/ETXD2/SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9 42 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 PIC32MX675F512H Vss 41 PIC32MX695F512H OSC2/CLKO/RC15 40 OSC1/CLKI/RC12 D+/RG2 37 D-/RG3 USB V 34 BUS USBID/RF3 Preliminary  2009 Microchip Technology Inc. ...

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... REF REF 15 PGED1/AN0/V +/CV +/PMA6/CN2/RB0 REF REF Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V externally. SS  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX = Pins are tolerant SOSCO/T1CK/CN0/RC14 48 47 SOSCI/CN1/RC13 OC1/INT0/RD0 46 45 ECRS/AERXCLK/IC4/PMCS1/PMA14/INT4/RD11 ECOL/AERXDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 44 43 ...

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... AN2/C2IN-/CN4/RB2 PGEC1/AN1/V -/CV -/CN3/RB1 15 REF REF PGED1/AN0/V +/CV +/PMA6/CN2/RB0 16 REF REF DS61156B-page PIC32MX575F256H PIC32MX575F512H Preliminary = Pins are tolerant 48 SOSCO/T1CK/CN0/RC14 47 SOSCI/CN1/RC13 46 OC1/INT0/RD0 45 IC4/PMCS1/PMA14/INT4/RD11 44 SCL1/IC3/PMCS2/PMA15/INT3/RD10 43 SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9 42 RTCC/IC1/INT1/RD8 41 Vss 40 OSC2/CLKO/RC15 39 OSC1/CLKI/RC12 D+/RG2 36 D-/RG3 V 35 USB 34 V BUS 33 USBID/RF3  2009 Microchip Technology Inc. ...

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... DD 10 AN5/C1IN+/V /CN7/RB5 BUSON 11 AN4/C1IN-/CN6/RB4 12 AN3/C2IN+/CN5/RB3 13 AN2/C2IN-/CN4/RB2 14 PGEC1/AN1/V -/CV -/CN3/RB1 REF REF 15 PGED1/AN0/V +/CV +/PMA6/CN2/RB0 16 REF REF  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX = Pins are tolerant SOSCO/T1CK/CN0/RC14 47 SOSCI/CN1/RC13 OC1/INT0/RD0 46 45 ECRS/AERXCLK/IC4/PMCS1/PMA14/INT4/RD11 ECOL/AERXDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 44 43 AERXD0/ETXD2/SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 42 41 Vss PIC32MX675F512H OSC2/CLKO/RC15 40 PIC32MX695F512H ...

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... AN4/C1IN-/CN6/RB4 12 AN3/C2IN+/CN5/RB3 13 AN2/C2IN- / CN4/RB2 14 PGEC1/AN1/V -/CV -/CN3/RB1 REF REF 15 PGED1/AN0/V +/CV +/PMA6/CN2/RB0 16 REF REF DS61156B-page SOSCO/T1CK/CN0/RC14 47 SOSCI/CN1/RC13 46 OC1/INT0/RD0 45 ECRS/AERXCLK/IC4/PMCS1/PMA14/INT4/RD11 ECOL/AERXDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 44 AERXD0/ETXD2/SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9 43 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 42 Vss 41 PIC32MX795F512H OSC2/CLKO/RC15 40 OSC1/CLKI/RC12 D+/RG2 37 D-/RG3 USB V 34 BUS USBID/RF3 Preliminary = Pins are tolerant  2009 Microchip Technology Inc. ...

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... MCLR 13 SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 TMS/RA0 17 INT1/RE8 18 INT2/RE9 19 AN5/C1IN+/V /CN7/RB5 20 BUSON AN4/C1IN-/CN6/RB4 21 AN3/C2IN+/CN5/RB3 22 AN2/C2IN-/CN4/RB2 23 PGEC1/AN1/CN3/RB1 24 PGED1/AN0/CN2/RB0 25  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX = Pins are tolerant PIC32MX575F512L PIC32MX575F256L Preliminary SOSCO/T1CK/CN0/RC14 73 SOSCI/CN1/RC13 72 SDO1/OC1/INT0/RD0 IC4/PMCS1/PMA14/RD11 71 SCK1/IC3/PMCS2/PMA15/RD10 70 69 SS1/ IC2 /RD9 68 RTCC/IC1/RD8 67 SDA1/INT4/RA15 66 SCL1/INT3/RA14 OSC2/CLKO/RC15 ...

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... PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 DS61156B-page PIC32MX675F512L 13 PIC32MX695F512L Preliminary = Pins are tolerant SOSCO/T1CK/CN0/RC14 73 SOSCI/CN1/RC13 72 SDO1/OC1/INT0/RD0 71 EMDC/IC4/PMCS1/PMA14/RD11 70 SCK1/IC3/PMCS2/PMA15/RD10 SS1/ IC2/RD9 69 68 RTCC/EMDIO/IC1/RD8 67 AETXEN/SDA1/INT4/RA15 AETXCLK/SCL1/INT3/RA14 OSC2/CLKO/RC15 OSC1/CLKI/RC12 TDO/RA5 TDI/RA4 60 SDA2/RA3 59 58 SCL2/RA2 D+/RG2 57 D-/RG3 USB V 54 BUS SCL1A/SDO1A/U1ATX/RF8 53 SDA1A/SDI1A/U1ARX/RF2 52 USBID/RF3 51  2009 Microchip Technology Inc. ...

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... AERXD0/INT1/RE8 18 AERXD1/INT2/RE9 19 AN5/C1IN+/V /CN7/RB5 20 BUSON AN4/C1IN-/CN6/RB4 21 AN3/C2IN+/CN5/RB3 22 AN2/C2IN-/CN4/RB2 23 PGEC1/AN1/CN3/RB1 24 PGED1/AN0/CN2/RB0 25  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX = Pins are tolerant PIC32MX795F512L Preliminary V SS SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0 EMDC/IC4/PMCS1/PMA14/RD11 SCK1/IC3/PMCS2/PMA15/RD10 SS1/ IC2 / RD9 RTCC/EMDIO/IC1/RD8 AETXEN/SDA1/INT4/RA15 AETXCLK/SCL1/INT3/RA14 V SS OSC2/CLKO/RC15 OSC1/CLKI/RC12 V DD TDO/RA5 ...

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... RE9 RA0 H RB5 RB4 RB3 RB2 RB7 K RB1 RB0 RA10 L RB6 RA9 AV SS Note 1: Refer to Table 2, Table 3, and Table 4 for full pin names. DS61156B-page 14 PIC32MX575F256L PIC32MX575F512L PIC32MX675F512L PIC32MX695F512L PIC32MX795F512L RE0 RG0 RF1 RE1 RA7 RF0 V / RD5 CAP V DDCORE RG14 RA6 NC RD7 ...

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... PMD7/RE7 D3 PMD5/RE5 Connect (NC) D7 PMD14/CN15/RD6 D8 PMD13/CN19/RD13 D9 SDO1/OC1/INT0/RD0 D10 No Connect (NC) D11 SCK1/IC3/PMCS2/PMA15/RD10 E1 T5CK/SDI1/RC4 E2 T4CK/RC3 E3 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 E4 T3CK/RC2 PMD9/RG1  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pin Number E8 SDA1/INT4/RA15 E9 RTCC/IC1/RD8 E10 SS1/IC2/RD9 E11 SCL1/INT3/RA14 F1 MCLR F2 SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 F3 SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 F4 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 Connect (NC Connect (NC OSC1/CLKI/RC12 F10 V SS F11 OSC2/CLKO/RC15 ...

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... Number K4 AN8/C1OUT/RB8 K5 No Connect (NC) K6 AC1RX/SS3A/U3BRX/U3ACTS/RF12 K7 AN14/PMALH/PMA1/RB14 SCK1A/U1BTX/U1ARTS/CN21/RD15 K10 USBID/RF3 K11 SDA1A/SDI1A/U1ARX/RF2 L1 PGEC2/AN6/OCFA/RB6 L2 V -/CV -/PMA7/RA9 REF REF DS61156B-page 16 Pin Number AN9/C2OUT/RB9 L5 AN10/CV /PMA13/RB10 REFOUT L6 AC1TX/SCK3A/U3BTX/U3ARTS/RF13 L7 AN13/PMA10/RB13 L8 AN15/OCFB/PMALL/PMA0/CN12/RB15 L9 SS1A/U1BRX/U1ACTS/CN20/RD14 L10 SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 L11 SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5 Preliminary  2009 Microchip Technology Inc. Full Pin Name ...

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... PMD5/RE5 Connect (NC) D7 ETXEN/PMD14/CN15/RD6 D8 ETXD3/PMD13/CN19/RD13 D9 SDO1/OC1/INT0/RD0 D10 No Connect (NC) D11 SCK1/IC3/PMCS2/PMA15/RD10 E1 T5CK/SDI1/RC4 E2 T4CK/RC3 E3 ECOL/SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 E4 T3CK/RC2 EXTERR/PMD9/RG1  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pin Full Pin Name Number E8 AETXEN/SDA1/INT4/RA15 E9 RTCC/EMDIO/IC1/RD8 E10 SS1/IC2/RD9 E11 AETXCLK/SCL1/INT3/RA14 F1 MCLR F2 ERXDV/SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 F3 ERXCLK/SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 F4 ECRS/SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 Connect (NC Connect (NC OSC1/CLKI/RC12 F10 V SS ...

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... Number K4 AN8/C1OUT/RB8 K5 No Connect (NC) K6 SS3A/U3BRX/U3ACTS/RF12 K7 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 AETXD1/SCK1A/U1BTX/U1ARTS/CN21/RD15 K10 USBID/RF3 K11 SDA1A/SDI1A/U1ARX/RF2 L1 PGEC2/AN6/OCFA/RB6 L2 V -/CV -/AERXD2/PMA7/RA9 REF REF DS61156B-page 18 Pin Full Pin Name Number AN9/C2OUT/RB9 L5 AN10/CV /PMA13/RB10 REFOUT L6 SCK3A/U3BTX/U3ARTS/RF13 L7 AN13/ERXD1/AECOL/PMA10/RB13 L8 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 L9 AETXD0/SS1A/U1BRX/U1ACTS/CN20/RD14 L10 SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 L11 SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5 Preliminary  2009 Microchip Technology Inc. ...

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... TABLE 4: PIN NAMES: PIC32MX795F512L DEVICE Pin Full Pin Name Number A1 PMD4/RE4 A2 PMD3/RE3 A3 TRD0/RG13 A4 PMD0/RE0 A5 C2RX/PMD8/RG0 A6 C1TX/ETXD0/PMD10/RF1 ETXD2/IC5/PMD12/RD12 A10 OC3/RD2 A11 OC2/RD1 B1 No Connect (NC) B2 AERXERR/RG15 B3 PMD2/RE2 B4 PMD1/RE1 B5 TRD3/RA7 B6 C1RX/ETXD1/PMD11/RF0 CAP DDCORE B8 PMRD/CN14/RD5 B9 OC4/RD3 B10 V SS B11 SOSCO/T1CK/CN0/RC14 C1 PMD6/RE6 TRD1/RG12 C4 TRD2/RG14 C5 TRCLK/RA6 ...

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... PIC32MX5XX/6XX/7XX TABLE 4: PIN NAMES: PIC32MX795F512L DEVICE Pin Full Pin Name Number K4 AN8/C1OUT/RB8 K5 No Connect (NC) K6 AC1RX/SS3A/U3BRX/U3ACTS/RF12 K7 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 AETXD1/SCK1A/U1BTX/U1ARTS/CN21/RD15 K10 USBID/RF3 K11 SDA1A/SDI1A/U1ARX/RF2 L1 PGEC2/AN6/OCFA/RB6 L2 V -/CV -/AERXD2/PMA7/RA9 REF REF DS61156B-page 20 Pin Full Pin Name Number AN9/C2OUT/RB9 L5 AN10/CV /PMA13/RB10 REFOUT L6 AC1TX/SCK3A/U3BTX/U3ARTS/RF13 L7 AN13/ERXD1/AECOL/PMA10/RB13 L8 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 L9 AETXD0/SS1A/U1BRX/U1ACTS/CN20/RD14 ...

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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Preliminary DS61156B-page 21 ...

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... PIC32MX5XX/6XX/7XX NOTES: DS61156B-page 22 Preliminary  2009 Microchip Technology Inc. ...

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... PORTG Note 1: Some features are not available on all device variants. 2: BOR functionality is provided when the on-board voltage regulator is enabled.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX This document contains device-specific information for PIC32MX5XX/6XX/7XX devices. Figure 1-1 shows a general block diagram of the core and peripheral modules in the PIC32MX5XX/6XX/7XX family of devices ...

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... Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. C10 I ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise. B11 O — 32.768 kHz low-power oscillator crystal output. Analog = Analog input O = Output Preliminary Description P = Power I = Input  2009 Microchip Technology Inc. ...

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... Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pin Buffer ...

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... PORTB is a bidirectional I/O port I/O ST PORTC is a bidirectional I/O port I/O ST C10 I/O ST B11 I/O ST F11 I/O ST Analog = Analog input O = Output Preliminary Description P = Power I = Input  2009 Microchip Technology Inc. ...

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... Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pin Buffer ...

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... L6 O — UART3A ready to send. L10 I ST UART3A receive. L11 O — UART3A transmit UART1B receive — UART1B transmit UART2B receive — UART2B transmit UART3B receive — UART3B transmit. Analog = Analog input O = Output Preliminary Description P = Power I = Input  2009 Microchip Technology Inc. ...

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... Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pin Buffer ...

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... L11 O — L10 O — — — — — C11 O — D11 O — C11 O — Parallel Master Port Chip Select 1 Strobe. D11 O — Parallel Master Port Chip Select 2 Strobe. Analog = Analog input O = Output Preliminary Description P = Power I = Input  2009 Microchip Technology Inc. ...

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... Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pin Buffer ...

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... Alternate Ethernet Transmit Enable. E11 I ST Alternate Ethernet Transmit Clock Alternate Ethernet Collision Detect Alternate Ethernet MII Carrier Sense — Trace Clock — Trace Data Bits 0- — — — Analog = Analog input O = Output Preliminary Description P = Power I = Input  2009 Microchip Technology Inc. ...

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... Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pin Buffer ...

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... PIC32MX5XX/6XX/7XX NOTES: DS61156B-page 34 Preliminary  2009 Microchip Technology Inc. ...

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... Note: The AV and connected, regardless of ADC use and the ADC voltage reference source.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 2.2 Decoupling Capacitors The use of decoupling capacitors on power supply pins, such as V See Figure 2-1. Consider the following criteria when using decoupling capacitors: • ...

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... Resets from brief glitches or to extend the device Reset period during POR. Preliminary ) and fast signal transitions must IL as shown in Figure 2- EXAMPLE OF MCLR PIN CONNECTIONS R R1 MCLR PIC32MX JP C and V specifications are met and V specifications are met. IL  2009 Microchip Technology Inc. ...

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... REAL ICE™ In-Circuit Debugger User's Guide” DS51616 ® • “Using MPLAB REAL ICE™” (poster) DS51749  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 2.6 JTAG The TMS, TDO, TDI, and TCK pins are used for testing and debugging according to the Joint Test Action Group (JTAG) standard ...

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... Unused I/O pins should not be allowed to float as inputs. They can be configured as outputs and driven Guard Ring to a logic-low state. Alternatively, inputs can be reserved by connecting the Main Oscillator pin to V through 10k resistor and configuring SS the pin as an input. Preliminary  2009 Microchip Technology Inc. ...

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... MCU BLOCK DIAGRAM MCU MDU Execution Core (RF/ALU/Shift) System Coprocessor  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX - Atomic interrupt enable/disable - GPR shadow registers to minimize latency for interrupt handlers - Bit field manipulation instructions • MIPS16e™ Code Compression - 16-bit encoding of 32-bit instructions to improve code density ...

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... Table 3-1 lists the repeat rate (peak issue rate of cycles until the operation can be reissued) and latency (num- ber of cycles until a result is available) for the PIC32MX core multiply and divide instructions. The approximate latency and repeat rates are listed in terms of pipeline clocks. Preliminary  2009 Microchip Technology Inc. ...

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... HI and LO registers. Similarly, the MSUB instruction multiplies two operands and then subtracts the product from the HI and LO registers. The MADD and MSUB operations are commonly used in DSP algorithms.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Operand Size (mul rt) (div rs) 16 bits 32 bits ...

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... DEPC Program counter at last debug exception. 25-29 Reserved Reserved in the PIC32MX5XX/6XX/7XX family core. (1) 30 ErrorEPC Program counter at last error. (2) 31 DESAVE Debug handler scratchpad register. Note 1: Registers used in exception processing. 2: Registers used during debug. DS61156B-page 42 Preliminary  2009 Microchip Technology Inc. ...

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... EJTAG Data Address Break (address only) or EJTAG Data Value Break on Store (address + value). AdEL Load address alignment error Load reference to protected address. AdES Store address alignment error. Store to protected address. DBE Load or store bus error. DDBL EJTAG data hardware breakpoint matched in load data compare.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Description Preliminary DS61156B-page 43 ...

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... Port (TAP), a serial communication port used for trans- ferring test data PIC32MX5XX/6XX/7XX family core. In addition to the standard JTAG instructions, special instructions defined in the EJTAG specification define which registers are selected and how they are used. Preliminary  2009 Microchip Technology Inc. in and out of the ...

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... Robust bus exception handling to intercept runaway code • Simple memory mapping with Fixed Mapping Translation (FMT) unit • Cacheable (KSEG0) and non-cacheable (KSEG1) address regions  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 4.1 PIC32MX5XX/6XX/7XX Memory Layout PIC32MX5XX/6XX/7XX microcontrollers implement two address schemes: virtual and physical. All hard- ...

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... DS61156B-page 46 Physical Memory Map Reserved (2) (2) Device Configuration Registers Boot Flash Reserved SFRs (2) Reserved Program Flash (2) Reserved RAM Preliminary 0xFFFFFFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF 0x1FC00000 0x1F900000 0x1F8FFFFF 0x1F800000 0x1D040000 0x1D03FFFF (2) 0x1D000000 0x00008000 0x00007FFF (2) 0x00000000  2009 Microchip Technology Inc. ...

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... Note 1: Memory areas are not shown to scale. 2: The size of this memory region is programmable (see Section 3. “Memory Organization” (DS61115)) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information).  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Physical Memory Map ...

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... PIC32MX5XX/6XX/7XX FIGURE 4-3: MEMORY MAP ON RESET FOR PIC32MX695F512H, PIC32MX695F512L, PIC32MX795F512H, AND PIC32MX795F512L DEVICES Virtual Memory Map 0xFFFFFFFF Reserved 0xBFC03000 0xBFC02FFF Device Configuration Registers 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 Reserved 0xBF900000 0xBF8FFFFF SFRs 0xBF800000 Reserved 0xBD080000 0xBD07FFFF Program Flash 0xBD000000 Reserved 0xA0020000 ...

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TABLE 4-1: BUS MATRIX REGISTER MAP 31/15 30/14 29/13 28/12 31:16 — — — — (1) BMXCON 2000 15:0 — — — — 31:16 — — — — (1) 2010 BMXDKPBA 15:0 31:16 — — — — (1) 2020 BMXDUDBA ...

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TABLE 4-2: INTERRUPT REGISTER MAP FOR THE PIC32MX575F256H AND PIC32MX575F512H DEVICES 31/15 30/14 29/13 28/12 31:16 — — — — 1000 INTCON 15:0 — FRZ — MVEC 31:16 — — — — INT- 1010 STAT 15:0 — — — — ...

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TABLE 4-2: INTERRUPT REGISTER MAP FOR THE PIC32MX575F256H AND PIC32MX575F512H DEVICES 31/15 30/14 29/13 28/12 31:16 — — — IPC2 10B0 15:0 — — — 31:16 — — — IPC3 10C0 15:0 — — — 31:16 — — — IPC4 ...

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TABLE 4-3: INTERRUPT REGISTER MAP FOR THE PIC32MX675F512H AND PIC32MX695F512H DEVICES 31/15 30/14 29/13 28/12 31:16 — — — — 1000 INTCON 15:0 — FRZ — MVEC 31:16 — — — — 1010 INTSTAT 15:0 — — — — 31:16 ...

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TABLE 4-3: INTERRUPT REGISTER MAP FOR THE PIC32MX675F512H AND PIC32MX695F512H DEVICES 31/15 30/14 29/13 28/12 31:16 — — — 10C0 IPC3 15:0 — — — 31:16 — — — 10D0 IPC4 15:0 — — — 31:16 — — — — ...

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TABLE 4-4: INTERRUPT REGISTER MAP FOR THE PIC32MX795F512H DEVICE 31/15 30/14 29/13 28/12 31:16 — — — — 1000 INTCON 15:0 — FRZ — MVEC 31:16 — — — — 1010 INTSTAT 15:0 — — — — 31:16 1020 IPTMR ...

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TABLE 4-4: INTERRUPT REGISTER MAP FOR THE PIC32MX795F512H DEVICE 31/15 30/14 29/13 28/12 31:16 — — — 10C0 IPC3 15:0 — — — 31:16 — — — 10D0 IPC4 15:0 — — — 31:16 — — — — 10E0 IPC5 ...

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TABLE 4-5: INTERRUPT REGISTER MAP FOR THE PIC32MX575F512L AND PIC32MX575F256L DEVICES 31/15 30/14 29/13 28/12 31:16 — — — — 1000 INTCON 15:0 — FRZ — MVEC 31:16 — — — — 1010 INTSTAT 15:0 — — — — 31:16 ...

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TABLE 4-5: INTERRUPT REGISTER MAP FOR THE PIC32MX575F512L AND PIC32MX575F256L DEVICES 31/15 30/14 29/13 28/12 31:16 — — — 10C0 IPC3 15:0 — — — 31:16 — — — 10D0 IPC4 15:0 — — — 31:16 — — — 10E0 ...

Page 58

TABLE 4-6: INTERRUPT REGISTER MAP FOR THE PIC32MX675F512L AND PIC32MX695F512L DEVICES 31/15 30/14 29/13 28/12 31:16 — — — — 1000 INTCON 15:0 — FRZ — MVEC 31:16 — — — — 1010 INTSTAT 15:0 — — — — 31:16 ...

Page 59

TABLE 4-6: INTERRUPT REGISTER MAP FOR THE PIC32MX675F512L AND PIC32MX695F512L DEVICES 31/15 30/14 29/13 28/12 31:16 — — — 10C0 IPC3 15:0 — — — 31:16 — — — 10D0 IPC4 15:0 — — — 31:16 — — — 10E0 ...

Page 60

... TABLE 4-7: INTERRUPT REGISTER MAP FOR THE PIC32MX795F512L DEVICE 31/15 30/14 29/13 28/12 31:16 — — — — 1000 INTCON 15:0 — FRZ — MVEC 31:16 — — — — 1010 INTSTAT 15:0 — — — — 31:16 1020 IPTMR 15:0 ...

Page 61

... TABLE 4-7: INTERRUPT REGISTER MAP FOR THE PIC32MX795F512L DEVICE 31/15 30/14 29/13 28/12 31:16 — — — 10C0 IPC3 15:0 — — — 31:16 — — — 10D0 IPC4 15:0 — — — 31:16 — — — 10E0 IPC5 15:0 — ...

Page 62

TABLE 4-8: TIMER1-TIMER5 REGISTER MAP 31/15 30/14 29/13 28/12 31:16 — — — — 0600 T1CON 15:0 ON FRZ SIDL TWDIS 31:16 — — — — 0610 TMR1 15:0 31:16 — — — — 0620 PR1 15:0 31:16 — — ...

Page 63

TABLE 4-9: INPUT CAPTURE1-INPUT CAPTURE5 REGISTER MAP 31/15 30/14 29/13 28/12 31:16 — — — (1) 2000 IC1CON 15:0 ON FRZ SIDL 31:16 2010 IC1BUF 15:0 31:16 — — — (1) 2200 IC2CON 15:0 ON FRZ SIDL 31:16 2210 IC2BUF ...

Page 64

TABLE 4-10: OUTPUT COMPARE 1-OUTPUT COMPARE 5 REGISTER MAP 31/15 30/14 29/13 28/12 31:16 — — — — 3000 OC1CON 15:0 ON FRZ SIDL — 31:16 3010 OC1R 15:0 31:16 3020 OC1RS 15:0 31:16 — — — — 3200 OC2CON ...

Page 65

TABLE 4-11: I2C1, I2C1A, I2C2A, AND I2C3A REGISTER MAP 31/15 30/14 29/13 28/12 31:16 — — — 5000 I2C1ACON 15:0 ON FRZ SIDL SCLREL 31:16 — — — 5010 I2C1ASTAT 15:0 ACKSTAT TRSTAT — 31:16 — — — 5020 I2C1AADD ...

Page 66

TABLE 4-11: I2C1, I2C1A, I2C2A, AND I2C3A REGISTER MAP 31/15 30/14 29/13 28/12 31:16 — — — 5220 I2C3AADD 15:0 — — — 31:16 — — — 5230 I2C3AMSK 15:0 — — — 31:16 — — — 5240 I2C3ABRG 15:0 ...

Page 67

... TABLE 4-12: I2C2 REGISTER MAP FOR PIC32MX575F512L, PIC32MX575F256L, PIC32MX675F512L, PIC32MX695F512L, AND PIC32MX795F512L DEVICES 31/15 30/14 29/13 28/12 31:16 — — — — 5400 I2C2CON 15:0 ON FRZ SIDL SCLREL 31:16 — — — — 5410 I2C2STAT 15:0 ACKSTAT TRSTAT — — 31:16 — ...

Page 68

TABLE 4-13: UART1A, UART1B, UART2A, UART2B, UART3A, AND UART3B REGISTER MAP 31/15 30/14 29/13 28/12 31:16 — — — (1) 6000 U1AMODE 15:0 ON FRZ SIDL IREN 31:16 — — — (1) 6010 U1ASTA 15:0 UTXISEL<1:0> UTXINV URXEN 31:16 — ...

Page 69

TABLE 4-13: UART1A, UART1B, UART2A, UART2B, UART3A, AND UART3B REGISTER MAP (CONTINUED) 31/15 30/14 29/13 28/12 31:16 — — — 6620 U2BTXREG 15:0 — — — 31:16 — — — 6630 U2BRXREG 15:0 — — — 31:16 — — — ...

Page 70

TABLE 4-14: SPI1A, SPI2A, AND SPI3A REGISTER MAP 31/15 30/14 29/13 28/12 31:16 FRMEN FRMSYNC FRMPOL MSSEN 5800 SPI1ACON 15:0 ON FRZ SIDL DISSDO 31:16 — — — 5810 SPI1ASTAT 15:0 — — — — 31:16 5820 SPI1ABUF 15:0 31:16 ...

Page 71

... TABLE 4-15: SPI1 REGISTER MAP FOR PIC32MX575F512L, PIC32MX575F256L, PIC32MX675F512L, PIC32MX695F512L AND PIC32MX795F512L DEVICES Register Name 31/15 30/14 29/13 28/12 31:16 FRMEN FRMSYNC FRMPOL MSSEN 5E00 SPI1CON 15:0 ON FRZ SIDL DISSDO 31:16 — — — 5E10 SPI1STAT 15:0 — — — 31:16 ...

Page 72

TABLE 4-16: ADC REGISTER MAP Register Name 31/15 30/14 29/13 28/12 31:16 — — — (1) 9000 AD1CON1 15:0 ON FRZ SIDL 31:16 — — — (1) 9010 AD1CON2 15:0 VCFG2 VCFG1 VCFG0 OFFCAL 31:16 — — — (1) 9020 ...

Page 73

TABLE 4-16: ADC REGISTER MAP (CONTINUED) Register Name 31/15 30/14 29/13 28/12 31:16 9120 ADC1BUFB 15:0 31:16 9130 ADC1BUFC 15:0 31:16 9140 ADC1BUFD 15:0 31:16 9150 ADC1BUFE 15:0 31:16 9160 ADC1BUFF 15:0 Legend unknown value on Reset; — ...

Page 74

TABLE 4-17: DMA GLOBAL REGISTER MAP 31/15 30/14 29/13 28/12 31:16 — — — (1) 3000 DMACON 15:0 ON FRZ — SUSPEND 31:16 — — — 3010 DMASTAT 15:0 — — — 31:16 3020 DMAADDR 15:0 Legend unknown ...

Page 75

TABLE 4-19: DMA CHANNELS 0-7 REGISTER MAP 31/15 30/14 29/13 28/12 31:16 — — — 3060 DCH0CON 15:0 CHBUSY — — 31:16 — — — 3070 DCH0ECON 15:0 31:16 — — — 3080 DCH0INT 15:0 — — — 31:16 3090 ...

Page 76

TABLE 4-19: DMA CHANNELS 0-7 REGISTER MAP 31/15 30/14 29/13 28/12 31:16 3160 DCH1DSA 15:0 31:16 — — — 3170 DCH1SSIZ 15:0 31:16 — — — 3180 DCH1DSIZ 15:0 31:16 — — — 3190 DCH1SPTR 15:0 31:16 — — — ...

Page 77

TABLE 4-19: DMA CHANNELS 0-7 REGISTER MAP 31/15 30/14 29/13 28/12 31:16 — — — 3270 DCH2CSIZ 15:0 31:16 — — — 3280 DCH2CPTR 15:0 31:16 — — — 3290 DCH2DAT 15:0 — — — 31:16 — — — 32A0 ...

Page 78

TABLE 4-19: DMA CHANNELS 0-7 REGISTER MAP 31/15 30/14 29/13 28/12 31:16 — — — 3380 DCH4INT 15:0 — — — 31:16 3390 DCH4SSA 15:0 31:16 33A0 DCH4DSA 15:0 31:16 — — — 33B0 DCH4SSIZ 15:0 31:16 — — — ...

Page 79

TABLE 4-19: DMA CHANNELS 0-7 REGISTER MAP 31/15 30/14 29/13 28/12 31:16 — — — 3490 DCH5SPTR 15:0 31:16 — — — 34A0 DCH5DPTR 15:0 31:16 — — — 34B0 DCH5CSIZ 15:0 31:16 — — — 34C0 DCH5CPTR 15:0 31:16 ...

Page 80

TABLE 4-19: DMA CHANNELS 0-7 REGISTER MAP 31/15 30/14 29/13 28/12 31:16 — — — 35A0 DCH7CON 15:0 CHBUSY — — 31:16 — — — 35B0 DCH7ECON 15:0 31:16 — — — 35C0 DCH7INT 15:0 — — — 31:16 35D0 ...

Page 81

TABLE 4-20: COMPARATOR REGISTER MAP 31/15 30/14 29/13 28/12 31:16 — — — A000 CM1CON 15:0 ON COE CPOL 31:16 — — — A010 CM2CON 15:0 ON COE CPOL 31:16 — — — A060 CMSTAT 15:0 — FRZ SIDL Legend: ...

Page 82

TABLE 4-22: FLASH CONTROLLER REGISTER MAP 31/15 30/14 29/13 28/12 31:16 — — — (1) F400 NVMCON 15:0 NVMWR NVMWREN NVMERR LVDERR 31:16 F410 NVMKEY 15:0 31:16 (1) F420 NVMADDR 15:0 31:16 F430 NVMDATA 15:0 31:16 NVMSRC F440 ADDR 15:0 ...

Page 83

... TABLE 4-24: PORT A REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F512L, PIC32MX695F512L, AND PIC32MX795F512L DEVICES 31/15 30/14 29/13 28/12 31:16 — — — — 6000 TRISA 15:0 TRISA15 TRISA14 — — 31:16 — — — — 6010 PORTA 15:0 RA15 RA14 — — ...

Page 84

... All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-27: PORT C REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F512L, PIC32MX695F512L, AND PIC32MX795F512L DEVICES 31/15 30/14 29/13 ...

Page 85

... All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-29: PORT D REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F512L, PIC32MX695F512L, AND PIC32MX795F512L DEVICES 31/15 30/14 29/13 ...

Page 86

... All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-31: PORT E REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F512L, PIC32MX695F512L, AND PIC32MX795F512L DEVICES 31/15 30/14 29/13 ...

Page 87

... All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-33: PORT F REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F512L, PIC32MX695F512L, AND PIC32MX795F512L DEVICES 31/15 30/14 29/13 ...

Page 88

... All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-35: PORT G REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F512L, PIC32MX695F512L, AND PIC32MX795F512L DEVICES 31/15 30/14 29/13 ...

Page 89

... TABLE 4-36: CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F512L, PIC32MX695F512L, AND PIC32MX795F512L DEVICES 31/15 30/14 29/13 28/12 31:16 — — — — 61C0 CNCON 15:0 ON FRZ SIDL — 31:16 — — — — 61D0 CNEN 15:0 CNEN15 CNEN14 ...

Page 90

TABLE 4-38: PARALLEL MASTER PORT REGISTER MAP 31/15 30/14 29/13 28/12 31:16 — — — — 7000 PMCON 15:0 ON FRZ SIDL ADRMUX<1:0> 31:16 — — — — 7010 PMMODE 15:0 BUSY IRQM<1:0> 31:16 — — — — 7020 PMADDR ...

Page 91

TABLE 4-40: PREFETCH REGISTER MAP 31/15 30/14 29/13 28/12 31:16 — — — (1,2) 4000 CHECON — — — 15:0 31:16 CHEWEN — — (1) 4010 CHEACC 15:0 — — — 31:16 LTAGBOOT — — (1) 4020 CHETAG 15:0 31:16 ...

Page 92

TABLE 4-41: RTCC REGISTER MAP 31/15 30/14 29/13 28/12 31:16 — — — 0200 RTCCON 15:0 ON FRZ SIDL 31:16 — — — 0210 RTCALRM 15:0 ALRMEN CHIME PIV ALRMSYNC 31:16 HR10<3:0> 0220 RTCTIME 15:0 SEC10<3:0> 31:16 YEAR10<3:0> 0230 ...

Page 93

TABLE 4-42: DEVCFG: DEVICE CONFIGURATION WORD SUMMARY 31/15 30/14 29/13 28/12 31:16 FVBUSIO FUSBIDIO FSCMIO — 2FF0 DEVCFG3 15:0 31:16 — — — — 2FF4 DEVCFG2 15:0 FUPLLEN — — — 31:16 — — — — 2FF8 DEVCFG1 15:0 FCKSM<1:0> ...

Page 94

TABLE 4-44: USB REGISTER MAP 31/15 30/14 29/13 28/12 31:16 — — — — 5040 U1OTGIR 15:0 — — — — 31:16 — — — — 5050 U1OTGIE 15:0 — — — — 31:16 — — — — 5060 U1OTGSTAT ...

Page 95

TABLE 4-44: USB REGISTER MAP (CONTINUED) 31/15 30/14 29/13 28/12 31:16 — — — — 5280 U1FRML 15:0 — — — — 31:16 — — — — 5290 U1FRMH 15:0 — — — — 31:16 — — — — 52A0 ...

Page 96

TABLE 4-44: USB REGISTER MAP (CONTINUED) 31/15 30/14 29/13 28/12 31:16 — — — — 5390 U1EP9 15:0 — — — — 31:16 — — — — 53A0 U1EP10 15:0 — — — — 31:16 — — — — 53B0 ...

Page 97

... TABLE 4-45: CAN1 REGISTER SUMMARY FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX795F512H, PIC32MX575F256L, PIC32MX575F512L, AND PIC32MX795F512L DEVICES 31/15 30/14 29/13 31:16 — — — B000 C1CON 15:0 ON — SIDLE 31:16 — — — C1CFG B010 15:0 SEG2PHTS SAM SEG1PH<2:0> 31:16 IVRIE WAKIE CERRIE SERRIE ...

Page 98

... TABLE 4-45: CAN1 REGISTER SUMMARY FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX795F512H, PIC32MX575F256L, PIC32MX575F512L, AND PIC32MX795F512L DEVICES 31/15 30/14 29/13 31:16 FLTEN19 MSEL19<1:0> C1FLTCON4 B100 15:0 FLTEN17 MSEL17<1:0> 31:16 FLTEN23 MSEL23<1:0> C1FLTCON5 B110 15:0 FLTEN21 MSEL21<1:0> 31:16 FLTEN27 MSEL27<1:0> C1FLTCON6 B120 15:0 FLTEN25 MSEL25<1:0> ...

Page 99

... TABLE 4-46: CAN2 REGISTER SUMMARY FOR PIC32MX795F512H AND PIC32MX795F512L DEVICES 31/15 30/14 29/13 28/12 31:16 — — — C000 C2CON 15:0 ON — SIDLE 31:16 — — — C010 C2CFG 15:0 SEG2PHTS SAM SEG1PH<2:0> 31:16 IVRIE WAKIE CERRIE SERRIE C020 C2INT 15:0 ...

Page 100

... TABLE 4-46: CAN2 REGISTER SUMMARY FOR PIC32MX795F512H AND PIC32MX795F512L DEVICES 31/15 30/14 29/13 28/12 31:16 FLTEN19 MSEL19<1:0> C100 C2FLTCON4 15:0 FLTEN17 MSEL17<1:0> 31:16 FLTEN23 MSEL23<1:0> C110 C2FLTCON5 15:0 FLTEN21 MSEL21<1:0> 31:16 FLTEN27 MSEL27<1:0> C120 C2FLTCON6 15:0 FLTEN25 MSEL25<1:0> 31:16 FLTEN31 MSEL31<1:0> ...

Page 101

... TABLE 4-47: ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX675F512H, PIC32MX695F512H, PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F512L, AND PIC32MX795F512L DEVICES 31/15 30/14 29/13 28/12 31:16 9000 ETHCON1 ON FRZ SIDL — 15:0 — — — — 31:16 9010 ETHCON2 — — — — 15:0 31:16 9020 ETHTXST ...

Page 102

... TABLE 4-47: ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX675F512H, PIC32MX695F512H, PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F512L, AND PIC32MX795F512L DEVICES 31/15 30/14 29/13 28/12 — — — — 31:16 90E0 ETHSTAT — — — — 15:0 — — — — ETH 31:16 9100 RXOV- 15:0 FLOW — ...

Page 103

... TABLE 4-47: ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX675F512H, PIC32MX695F512H, PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F512L, AND PIC32MX795F512L DEVICES 31/15 30/14 29/13 28/12 — — — — 31:16 EMACx 9260 SUPP — — — — 15:0 — — — — 31:16 EMACx 9270 TEST — ...

Page 104

... PIC32MX5XX/6XX/7XX NOTES: DS61156B-page 104 Preliminary  2009 Microchip Technology Inc. ...

Page 105

... Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX PIC32MX5XX/6XX/7XX devices contain an internal Flash program memory for executing user code. There are three methods by which the user can program this memory: 1 ...

Page 106

... PIC32MX5XX/6XX/7XX NOTES: DS61156B-page 106 Preliminary  2009 Microchip Technology Inc. ...

Page 107

... DD Detect Configuration Mismatch Reset Software Reset  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX The Reset module combines all Reset sources and controls the device Master Reset signal, SYSRST. The following is a list of device Reset sources: • POR: Power-on Reset • MCLR: Master Clear Reset Pin • ...

Page 108

... PIC32MX5XX/6XX/7XX NOTES: DS61156B-page 108 Preliminary  2009 Microchip Technology Inc. ...

Page 109

... CPU logic and prioritizes the interrupt events before presenting them to the CPU. FIGURE 7-1: INTERRUPT CONTROLLER MODULE Interrupt Controller  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX The PIC32MX5XX/6XX/7XX interrupt module includes the following features: • Interrupt Sources • Interrupt Vectors • ...

Page 110

... IPC3<12:10> IPC3<9:8> IPC3<20:18> IPC3<17:16> IPC3<28:26> IPC3<25:24> IPC4<4:2> IPC4<1:0> IPC4<12:10> IPC4<9:8> IPC4<20:18> IPC4<17:16> IPC4<28:26> IPC4<25:24> IPC5<4:2> IPC5<1:0> IPC5<12:10> IPC5<9:8> IPC5<20:18> IPC5<17:16> IPC5<28:26> IPC5<25:24> IPC5<28:26> IPC5<25:24> IPC5<28:26> IPC5<25:24> IPC6<4:2> IPC6<1:0> IPC6<4:2> IPC6<1:0> IPC6<4:2> IPC6<1:0> IPC6<12:10> IPC6<9:8> IPC6<12:10> IPC6<9:8>  2009 Microchip Technology Inc. ...

Page 111

... CAN1 – Control Area Network 1 CAN2 – Control Area Network 2 ETH – Ethernet Interrupt Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX Features” for the list of available peripherals.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Interrupt Bit Location Vector IRQ Number ...

Page 112

... Lowest Natural Order Priority Preliminary Priority Sub-Priority IPC1<12:10> IPC1<9:8> IPC2<12:10> IPC2<9:8> IPC3<12:10> IPC3<9:8> IPC4<12:10> IPC4<9:8> IPC5<12:10> IPC5<9:8> IPC7<4:2> IPC7<1:0> IPC12<12:10> IPC12<9:8> IPC12<12:10> IPC12<9:8> IPC12<12:10> IPC12<9:8> IPC12<20:18> IPC12<17:16> IPC12<20:18> IPC12<17:16> IPC12<20:18> IPC12<17:16> IPC12<28:26> IPC12<25:24> — —  2009 Microchip Technology Inc. ...

Page 113

... Family Reference Manual” for help in determining the best oscillator components. 4. PBCLK out is available on the OSC2 pin in certain clock modes.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX The PIC32MX5XX/6XX/7XX oscillator system has the following modules and features: • A Total of Four External and Internal Oscillator Options as Clock Sources • ...

Page 114

... PIC32MX5XX/6XX/7XX NOTES: DS61156B-page 114 Preliminary  2009 Microchip Technology Inc. ...

Page 115

... Cache Ctrl Prefetch Ctrl Hit LRU Miss LRU Hit Logic PreFetch Pre-Fetch  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Prefetch cache increases performance for applications executing out of the cacheable program Flash memory regions by implementing instruction caching, constant data caching and instruction prefetching. 9.1 Features • ...

Page 116

... PIC32MX5XX/6XX/7XX NOTES: DS61156B-page 116 Preliminary  2009 Microchip Technology Inc. ...

Page 117

... DMA BLOCK DIAGRAM INT Controller System IRQ Peripheral Bus Address Decoder Global Control (DMACON)  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX • Automatic Word-Size Detection: - Transfer Granularity, down to byte level - Bytes need not be word-aligned at source and destination • Fixed Priority Channel Arbitration • ...

Page 118

... PIC32MX5XX/6XX/7XX NOTES: DS61156B-page 118 Preliminary  2009 Microchip Technology Inc. ...

Page 119

... Interface Engine (SIE), a dedicated USB DMA control- ler, pull-up and pull-down resistors, and the register interface. A block diagram of the PIC32MX USB OTG module is presented in Figure 11-1.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX The clock generator provides the 48 MHz clock required for USB full-speed and low-speed communi- cation ...

Page 120

... To Clock Generator for Core and Peripherals USB Suspend Sleep or Idle USB Voltage Comparators SIE Transceiver Preliminary FRC Oscillator 8 MHz Typical (4) TUN<5:0> Div 2 (3) UFRCEN (6) FUPLLEN USB Module (7) 48 MHz USB Clock Registers and Control Interface DMA System RAM  2009 Microchip Technology Inc. ...

Page 121

... This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure for any specific port/peripheral combination may be different than it is shown here.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX General purpose I/O pins are the simplest of peripher- als ...

Page 122

... CV output voltage used by the comparator REF module. Configuring the comparator reference module to provide this output will present the analog output voltage on the pin, independent of the TRIS register setting for the corresponding pin. Preliminary specification. Refer  2009 Microchip Technology Inc. ...

Page 123

... SOSCEN SOSCI Note 1: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in Configuration Word DEVCFG1.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX This family of PIC32MX devices features one synchronous/asynchronous 16-bit timer that can oper- ate as a free-running interval timer for various timing applications and counting external events ...

Page 124

... PIC32MX5XX/6XX/7XX NOTES: DS61156B-page 124 Preliminary  2009 Microchip Technology Inc. ...

Page 125

... TxCK Note 1: ADC event trigger is available on Timer3 only. 2: TxCK pins are not available on 64-pin devices.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Two 32-bit synchronous timers are available by combining Timer2 with Timer3 and Timer4 with Timer5. The 32-bit timers can operate in three modes: • ...

Page 126

... TxCK pins are not available on 64-pin devices. 3: ADC event trigger is available only on the Timer2/3 pair. DS61156B-page 126 TMRx Sync LSHalfWord PRx Gate 1 0 Sync PBCLK 0 0 Preliminary TGATE (TxCON<7>) TCS (TxCON<1>) ON (TxCON<15>) Prescaler 16, 32, 64, 256 3 TCKPS (TxCON<6:4>)  2009 Microchip Technology Inc. ...

Page 127

... INPUT CAPTURE BLOCK DIAGRAM ICx Input Prescaler Edge Detect ICM<2:0> ICM<2:0> ICFEDGE ICxCON  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 2. Capture timer value on every edge (rising and falling) 3. Capture timer value on every edge (rising and falling), specified edge first. 4. Prescaler Capture Event modes ...

Page 128

... PIC32MX5XX/6XX/7XX NOTES: DS61156B-page 128 Preliminary  2009 Microchip Technology Inc. ...

Page 129

... The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel. 3: Each output compare channel can use one of two selectable 16-bit time bases or a single 32-bit timer base.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX The Output Compare module (OCMP) is used to gen- erate a single pulse or a train of pulses in response to selected time base events ...

Page 130

... PIC32MX5XX/6XX/7XX NOTES: DS61156B-page 130 Preliminary  2009 Microchip Technology Inc. ...

Page 131

... Sync Control SSx/F SYNC SCKx Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX The SPI module is a synchronous serial interface that is useful for communicating with external peripherals and other microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, dis- play drivers, A/D converters, etc ...

Page 132

... PIC32MX5XX/6XX/7XX NOTES: DS61156B-page 132 Preliminary  2009 Microchip Technology Inc. ...

Page 133

... Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 2 The I C module provides complete hardware support for both Slave and Multi-Master modes of the I communication standard ...

Page 134

... Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSB Reload Control PBCLK Preliminary Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read  2009 Microchip Technology Inc. ...

Page 135

... UARTx Receiver UARTx Transmitter Note: Not all pins are available for all UART modules. Refer to the device-specific pin diagram for more information.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX The primary features of the UART module are: • Full-duplex, 8-bit or 9-bit Data Transmission • ...

Page 136

... Clock) UxTX Start UxTXIF UTXISEL = 00 UxTXIF UTXISEL = 01 UxTXIF UTXISEL = 10 DS61156B-page 136 Char 11-13 Char 5-10 Stop 4 Start 5 Stop 10 Start 11 Pull from Buffer bit 0 bit 1 Preliminary Stop 13 Cleared by software Cleared by software Cleared by software Stop Start Bit 1  2009 Microchip Technology Inc. ...

Page 137

... PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES PIC32MX5XX/6XX/7XX Parallel Master Port Note 1: On 64-pin devices, data pins PMD<15:8> are not available in 16-bit Master modes.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Key features of the PMP module include: • 8-bit, 16-bit Interface • Programmable Address Lines • ...

Page 138

... PIC32MX5XX/6XX/7XX NOTES: DS61156B-page 138 Preliminary  2009 Microchip Technology Inc. ...

Page 139

... Alarm Event Comparator Compare Registers with Masks Repeat Counter  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Following are some of the key features of this module: • Time: Hours, Minutes and Seconds • 24-Hour Format (Military Time) • Visibility of One-Half-Second Period • Provides Calendar: Weekday, Date, Month and Year • ...

Page 140

... PIC32MX5XX/6XX/7XX NOTES: DS61156B-page 140 Preliminary  2009 Microchip Technology Inc. ...

Page 141

... Note inputs can be multiplexed with other analog inputs. REF REF  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX • One Unipolar, Differential Sample-and-Hold Amplifier (SHA) • Automatic Channel Scan mode • Selectable Conversion Trigger Source • 16-word Conversion Result Buffer • Selectable Buffer Fill modes • ...

Page 142

... PIC32MX5XX/6XX/7XX FIGURE 22-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM FRC Div DS61156B-page 142 ADCS<7:0> 8 ADC Conversion Clock Multiplier 2, 4,..., 512 Preliminary  2009 Microchip Technology Inc. ADRC ...

Page 143

... Masks CxRX CAN Module Message Buffer 31 Message Buffer 1 Message Buffer 0 FIFO0  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX - Each FIFO can have messages for a total of 1024 messages - FIFO can be a transmit message FIFO or a receive message FIFO - User-defined priority levels for message ...

Page 144

... PIC32MX5XX/6XX/7XX NOTES: DS61156B-page 144 Preliminary  2009 Microchip Technology Inc. ...

Page 145

... RX Bus Master DMA Control Registers Ethernet Controller  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX • Supports 10/100 Mbps Data Transfer Rates • Supports Full-Duplex and Half-Duplex Operation • Supports RMII and MII PHY Interface • Supports MIIM PHY Management Interface • Supports both Manual and Automatic Flow Con- trol • ...

Page 146

... PIC32MX5XX/6XX/7XX NOTES: DS61156B-page 146 Preliminary  2009 Microchip Technology Inc. ...

Page 147

... Note 1: On devices with a USB module, and when the module is enabled, this pin is controlled by the USB module and therefore is not available as a comparator input. 2: Internally connected.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX The PIC32MX5XX/6XX/7XX analog comparator mod- ule contains two comparators that can be configured in a variety of ways ...

Page 148

... PIC32MX5XX/6XX/7XX NOTES: DS61156B-page 148 Preliminary  2009 Microchip Technology Inc. ...

Page 149

... Steps CVRR CVRSS = REF AV SS CVRSS = 0  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX The CV module is a 16-tap, resistor ladder network REF that provides a selectable reference voltage. Although ) its primary purpose is to provide a reference for the analog comparators, it also may be used independently of them. ...

Page 150

... PIC32MX5XX/6XX/7XX NOTES: DS61156B-page 150 Preliminary  2009 Microchip Technology Inc. ...

Page 151

... FRC Idle mode: the system clock is derived from the FRC with or without postscalers. Peripherals continue to operate, but can option- ally be individually disabled.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX • S Idle mode: the system clock is derived from OSC the S ...

Page 152

... PBCLK divider, peripheral clock require- ments such as baud rate accuracy should be taken into account. For example, the UART peripheral may not be able to achieve all baud rate values at some PBCLK divider depending on the SYSCLK value. Preliminary  2009 Microchip Technology Inc. ...

Page 153

... These are: • Flexible Device Configuration • Watchdog Timer • JTAG Interface • In-Circuit Serial Programming™ (ICSP™) 28.1 Configuration Bits The Configuration bits can be programmed to select various device configurations.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX several Preliminary DS61156B-page 153 ...

Page 154

... R/P-1 R/P-1 — PWP<7:4> R/P-1 r-1 r-1 — — r-1 R/P-1 r-1 — ICESEL — Programmable bit Preliminary  2009 Microchip Technology Inc. r-1 R/P-1 — BWP bit 24 R/P-1 R/P-1 bit 16 r-1 r-1 — — bit 8 R/P-1 R/P-1 DEBUG<1:0> bit 0 ...

Page 155

... PGEC1/PGED1 pair is used bit 2 Reserved: Write ‘ 1 ’ bit 1-0 DEBUG<1:0>: Background Debugger Enable bits (forced to ‘ 11 ’ if code-protect is enabled Debugger disabled 10 = Debugger enabled 01 = Reserved (same as ‘ 11 ’ setting Reserved (same as ‘ 11 ’ setting)  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Preliminary DS61156B-page 155 ...

Page 156

... WDTPS<4:0> R/P-1 r-1 FPBDIV<1:0> — OSCIOFNC r-1 r-1 — — Programmable bit Preliminary r-1 r-1 r-1 — — — bit 24 R/P-1 R/P-1 R/P-1 bit 16 R/P-1 R/P-1 R/P-1 POSCMD<1:0> bit 8 R/P-1 R/P-1 R/P-1 FNOSC<2:0> bit Reserved bit  2009 Microchip Technology Inc. ...

Page 157

... Primary Oscillator with PLL module (XT+PLL, HS+PLL, EC+PLL) 100 = Secondary Oscillator (S 101 = Low-Power RC Oscillator (LPRC) 110 = FRCDIV16 Fast RC Oscillator with fixed divide-by-16 postscaler 111 = Fast RC Oscillator with divide-by-N (FRCDIV) Note 1: Do not disable P  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX (1) ) OSC (POSCMD = 00 ) when using this oscillator source. OSC ...

Page 158

... R/P-1 — — FPLLODIV<2:0> r-1 r-1 R/P-1 — — FUPLLIDIV<2:0> R/P-1 r-1 R/P-1 — Programmable bit Preliminary  2009 Microchip Technology Inc. r-1 r-1 — — bit 24 R/P-1 R/P-1 bit 16 R/P-1 R/P-1 bit 8 R/P-1 R/P-1 FPLLIDIV<2:0> bit Reserved bit ...

Page 159

... Reserved: Write ‘ 1 ’ bit 2-0 FPLLIDIV<2:0>: PLL Input Divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Preliminary DS61156B-page 159 ...

Page 160

... FCANIO r-1 r-1 R/P-1 — — FSRSSEL<2:0> R/P-x R/P-x R/P-x USERID<15:8> R/P-x R/P-x R/P-x USERID<7:0> Programmable bit Preliminary  2009 Microchip Technology Inc. R/P-1 R/P-1 FETHIO FMIIEN bit 24 R/P-1 R/P-1 bit 16 R/P-x R/P-x bit 8 R/P-x R/P-x bit Reserved bit ...

Page 161

... U = Unimplemented bit -n = Bit Value at POR: (‘0’, ‘1’ Unknown) bit 31-28 VER<3:0>: Revision Identifier bits bit 27-0 DEVID<27:0>: Device ID Note: See the “PIC32MX Flash Programming Specification” (DS61145) for a list of Revision and Device ID values.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX DEVID<23:16> ...

Page 162

... LPRC Oscillator WDTCLR = 1 WDT Enable Wake WDT Enable Reset Event DS61156B-page 162 1:64 Output 1 Clock 25-bit Counter 25 WDT Counter Reset Decoder FWDTPS<4:0>(DEVCFG1<20:16>) Preliminary LPRC Control PWRT Enable PWRT Device Reset 0 1 NMI (Wake-up) Power Save  2009 Microchip Technology Inc. ...

Page 163

... Reset circuitry will generate a Brown-out Reset. This event is captured by the BOR flag bit (RCON<1>). The brown-out voltage levels are specific in Section 31.1 “DC Characteristics” .  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 28.3.3 POWER-UP REQUIREMENTS The on-chip regulator is designed to meet the power-up requirements for the device ...

Page 164

... TRD2 TRD3 DS61156B-page 164 PIC32MX devices incorporate two programming and diagnostic modules, and a trace controller, that provide a range of functions to the application developer. ICSP™ Controller ICESEL JTAG Controller JTAGEN DEBUG<1:0> Instruction Trace Controller DEBUG<1:0> Preliminary Core  2009 Microchip Technology Inc. ...

Page 165

... JTAGEN: JTAG Port Enable bit 1 = Enable JTAG Port 0 = Disable JTAG Port bit 2 TROEN: Trace Output Enable bit 1 = Enable Trace Port 0 = Disable Trace Port bit 1-0 Reserved: Write ‘ 1 ’; ignore read  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX r-x r-x r-x — — — r-x ...

Page 166

... PIC32MX5XX/6XX/7XX NOTES: DS61156B-page 166 Preliminary  2009 Microchip Technology Inc. ...

Page 167

... Branch on Greater Than Zero Likely BGTZL Branch on Less Than or Equal to Zero BLEZ Note 1: This instruction is deprecated and should not be used.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Table 29-1 provides a summary of the instructions that are implemented by the PIC32MX5XX/6XX/7XX family core. Note: Refer to “MIPS32 grammers Volume II: The MIPS32 Instruction Set” ...

Page 168

... Rt = Status; Status if StatusERL[2] else StatusERL[ ExtractField(Rs, pos, size) Preliminary Function PC += (int)offset Ignore Next Instruction PC += (int)offset PC += (int)offset PC += (int)offset Ignore Next Instruction PC += (int)offset Ignore Next Instruction PC += (int)offset PC += (int)offset Ignore Next Instruction = ErrorEPC PC = EPC StatusEXL[  2009 Microchip Technology Inc. ...

Page 169

... Multiply with register write MUL Integer Multiply MULT Unsigned Multiply MULTU No Operation (Assembler idiom for: SLL r0, r0, r0) NOP Note 1: This instruction is deprecated and should not be used.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Description Rt = InsertField(Rs, Rt, pos, size PC[31:28] || offset<<2 GPR[31 PC[31:28] || offset<< ...

Page 170

... Rd = (int)Rt >> (int)Rt >> Rs[4: (uns)Rt >> (uns)Rt >> Rs[4:0] NOP Rt = (int)Rs - (int) (uns)Rs - (uns)Rd Mem[Rs+offset Mem[Rs+offset Mem[Rs+offset Preliminary Function , Rd] PSS || Rt sa-1..0 31.. Rs-1..0 31..Rs mem[Rs+offset>  2009 Microchip Technology Inc. ...

Page 171

... Word Swap Bytes Within Halfwords WSBH Exclusive OR XOR Exclusive OR Immediate XORI Note 1: This instruction is deprecated and should not be used.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Description Orders the cached coherent and uncached loads and stores for access to shared memory SystemCallException (int)Immed if (int)Rs > ...

Page 172

... PIC32MX5XX/6XX/7XX NOTES: DS61156B-page 172 Preliminary  2009 Microchip Technology Inc. ...

Page 173

... MPLAB ICD 3 - PICkit™ 3 Debug Express • Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 30.1 MPLAB Integrated Development Environment Software ® digital signal The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market ...

Page 174

... Support for the entire device instruction set ® standard HEX • Support for fixed-point and floating-point data • Command line interface • Rich directive set • Flexible macro language • MPLAB IDE compatibility Preliminary  2009 Microchip Technology Inc. ...

Page 175

... Microchip Technology Inc. PIC32MX5XX/6XX/7XX 30.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Micro- chip's most cost effective high-speed hardware ...

Page 176

... This usually includes a single application and debug capability, all for DDMAX on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. Preliminary ® L security ICs, CAN ®  2009 Microchip Technology Inc. ...

Page 177

... Exposure to maximum rating conditions for extended periods may affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table 31-2). 3: See the “Pin Diagrams” section for the 5V tolerant pins.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX (Note 3) ......................................... -0.  ...

Page 178

... MHz (Note 1) Min. Typical Max. Unit -40 — +125 °C -40 — +85 ° INT  (T – Max. Unit Notes 40 — °C — °C — °C — °C — °C/W 1 -40°C  T  +85°C for Industrial A Units Conditions  s  2009 Microchip Technology Inc. ...

Page 179

... Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated. Parameters are for design guidance only and are not tested. 4: This parameter is characterized, but not tested in manufacturing.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) -40° ...

Page 180

... System clock is enabled and DLE . Preliminary  +85°C for Industrial A Conditions 4 MHz 25 MHz (Note 3) 60 MHz (Note 3) 80 MHz 2.3V LPRC (31 kHz) 3.3V (Note 3) 3.6V  2009 Microchip Technology Inc. ...

Page 181

... Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled. 5: Data is characterized at +70°C and not tested. Parameter is for design guidance only. 6: This parameter is characterized, but not tested in manufacturing.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) -40°C  T  +85°C for Industrial ...

Page 182

... V  5.5 PIN (Note 4)  3.3V PIN SS  A  V  PIN DD Pin at high-impedance  A  V  PIN DD Pin at high-impedance  A  V  PIN DD  A  V  PIN DD XT and HS modes  2009 Microchip Technology Inc. ...

Page 183

... Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The default Arbitration mode is mode 1 (CPU has lowest priority). 3: Refer to “PIC32MX Flash Programming Specification” (DS61145) for operating conditions during programming and erase cycles.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) -40°C  T  ...

Page 184

... DD Preliminary Comments  +85°C for Industrial A Units Comments (Note 2) dB Max 1)V ICM DD (Note (Notes 1, 2)  s Comparator module is configured before setting the comparator ON bit. (Note 2)  2009 Microchip Technology Inc. ...

Page 185

... Regulator Output Voltage DDCORE D321 C External Filter Capacitor Value EFC D322 T Power-up Timer Period PWRT  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature-40°C  T  +85°C for Industrial A Min. Typical Max. Units ...

Page 186

... T Operating temperature (1) Min. Typical Max. Units — — — — 400 pF OS30 OS30 Preliminary -40°C  T  +85°C for Industrial A range  +85°C for Industrial A Conditions EC mode C™ mode OS31 OS31  2009 Microchip Technology Inc. ...

Page 187

... MHz maximum for PIC32MX 40 MHz family variants. 4: PLL input requirements characterized, but tested at 10 MHz only at manufacturing. 5: This parameter is characterized, but not tested in manufacturing.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature (1) Min. ...

Page 188

... Industrial A Min. Typical Max. Units -15 — +15 % changes. DD Preliminary  +85°C for Industrial A Units Conditions 5 MHz ECPLL, HSPLL, XTPLL, FRCPLL modes MHz Measured over 100 ms period  TA +85°C for industrial Conditions Conditions  2009 Microchip Technology Inc. ...

Page 189

... T CNx High or Low Time (input) RBP Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. 2: This parameter is characterized, but not tested in manufacturing.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX DI35 DI40 DO31 DO32 Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) -40° ...

Page 190

... Power-Up Timer (PWRT); only active when the internal voltage regulator is disabled. DS61156B-page 190 SYSDLY SY02 CPU starts fetching code SY00 ( (Note 1) ) OSC SYSDLY SY02 CPU starts fetching code SY00 SY10 ( OST (Note DDCORE (T ) SYSDLY SY02 CPU starts fetching code SY01 (T ) PWRT (Note 1) < DDMIN Preliminary  2009 Microchip Technology Inc. ...

Page 191

... MCLR SY30 T BOR Pulse Width (low) BOR Note 1: These parameters are characterized, but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Characterized by design but not tested.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX T MCLR (SY20) T BOR (T ) SYSDLY ...

Page 192

... N] — — [( — — 32 — — Preliminary Tx20 (1)  +85°C for Industrial A Conditions — ns Must also meet parameter TA15. — ns — ns Must also meet parameter TA15. — ns — ns — prescale value (1, 8, 64, 256) 100 kHz  2009 Microchip Technology Inc. ...

Page 193

... ICx Input Low Time CC IC11 T H ICx Input High Time CC IC15 T P ICx Input Period CC Note 1: These parameters are characterized, but not tested in manufacturing.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) -40°C  T Operating temperature (1) Min. [(12 [(12 ...

Page 194

... Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature (1) (2) Min Typical — — 50 — Preliminary  +85°C for Industrial A Units Conditions ns See parameter DO32. ns See parameter DO31. -40°C  T  +85°C for Industrial A Max Units Conditions 50 ns — ns  2009 Microchip Technology Inc. ...

Page 195

... Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX SP10 SP21 SP20 SP21 SP20 ...

Page 196

... Preliminary SP20 SP21 -40°C  T  +85°Cfor Industrial A Max. Units Conditions — ns — ns — ns See parameter DO32. ns — See parameter DO31. ns — See parameter DO32. ns — See parameter DO31 — ns — ns — ns  2009 Microchip Technology Inc. ...

Page 197

... Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCKx is 40 ns. 4: Assumes 50 pF load on all SPIx pins.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX SP70 SP73 SP72 SP73 ...

Page 198

... T /2 — SCK — 5 — 5 — — — — — — — 10 — 10 Preliminary SP52 SP51 -40°C  T  +85°C for Industrial A Units Conditions — ns — — ns See parameter DO32. — ns See parameter DO31 — ns — ns  2009 Microchip Technology Inc. ...

Page 199

... Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCKx is 40 ns. 4: Assumes 50 pF load on all SPIx pins.  2009 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature (1) (2) Min ...

Page 200

... I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 SCLx IM11 IM10 SDAx In IM40 SDAx Out Note: Refer to Figure 31-1 for load conditions. DS61156B-page 200 IM11 IM10 IM26 IM25 IM40 Preliminary IM34 IM33 Stop Condition IM21 IM33 IM45  2009 Microchip Technology Inc. ...