PIC32MX795F512L-80I/PF Microchip Technology, PIC32MX795F512L-80I/PF Datasheet - Page 115

• Manufacturer Part Number: PIC32MX795F512L-80I/PF
• Description: IC MCU 32BIT 512KB FLASH 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX795F512L-80I/PF

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: MIPS32® M4K™
• Speed: 80MHz
• Connectivity: CAN, Ethernet, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Controller Family/series: PIC32
• Ram Memory Size: 128KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Interface: CAN, I2C, SPI, UART, USB
• No. Of Pwm Channels: 5
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: PIC32MX7xx
• Core: MIPS
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

9.0
FIGURE 9-1:
 2009 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
2: Some registers and associated bits
PREFETCH CACHE
CTRL
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 4. “Prefetch
Cache” (DS61119) in the “PIC32MX
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
described in this section may not be avail-
able
4.0 “Memory Organization” in this data
sheet for device-specific register and bit
information.
Prefetch Ctrl
Cache Ctrl
Miss LRU
Bus Ctrl
Hit LRU
on
FSM
PREFETCH MODULE BLOCK DIAGRAM
all
devices.
Tag Logic
PreFetch
Pre-Fetch
Hit Logic
Tag
Refer
PFM
Preliminary
Address
Encode
to
Cache
Line
PIC32MX5XX/6XX/7XX
CTRL
Prefetch cache increases performance for applications
executing out of the cacheable program Flash memory
regions by implementing instruction caching, constant
data caching and instruction prefetching.
9.1
• 16 Fully Associative Lockable Cache Lines
• 16-byte Cache Lines
• Up to four Cache Lines Allocated to Data
• Two Cache Lines with Address Mask to Hold
• Pseudo LRU Replacement Policy
• All Cache Lines are Software Writable
• 16-byte Parallel Memory Fetch
• Predictive Instruction Prefetch
Repeated Instructions
Cache Line
Pre-Fetch
Features
PreFetch
RDATA
DS61156B-page 115