PIC32MX795F512L-80I/PF Microchip Technology, PIC32MX795F512L-80I/PF Datasheet - Page 170

• Manufacturer Part Number: PIC32MX795F512L-80I/PF
• Description: IC MCU 32BIT 512KB FLASH 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX795F512L-80I/PF

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: MIPS32® M4K™
• Speed: 80MHz
• Connectivity: CAN, Ethernet, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Controller Family/series: PIC32
• Ram Memory Size: 128KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Interface: CAN, I2C, SPI, UART, USB
• No. Of Pwm Channels: 5
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: PIC32MX7xx
• Core: MIPS
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC32MX5XX/6XX/7XX
TABLE 29-1:
DS61156B-page 170
NOR
OR
ORI
RDHWR
RDPGPR
ROTR
ROTRV
SB
SC
SDBBP
SEB
SEH
SH
SLL
SLLV
SLT
SLTI
SLTIU
SLTU
SRA
SRAV
SRL
SRLV
SSNOP
SUB
SUBU
SW
SWL
SWR
Note 1:
Instruction
This instruction is deprecated and should not be used.
Logical NOR
Logical OR
Logical OR Immediate
Read Hardware Register (if enabled by HWREna register)
Read GPR from Previous Shadow Set
Rotate Word Right
Rotate Word Right Variable
Store Byte
Store Conditional Word
Software Debug Break Point
Sign-Extend Byte
Sign-Extend Half
Store Half
Shift Left Logical
Shift Left Logical Variable
Set on Less Than
Set on Less Than Immediate
Set on Less Than Immediate Unsigned
Set on Less Than Unsigned
Shift Right Arithmetic
Shift Right Arithmetic Variable
Shift Right Logical
Shift Right Logical Variable
Superscalar Inhibit No Operation
Integer Subtract
Unsigned Subtract
Store Word
Store Word Left
Store Word Right
MIPS32
®
INSTRUCTION SET (CONTINUED)
Description
Preliminary
Rd = ~(Rs | Rt)
Rd = Rs | Rt
Rt = Rs | Immed
Rt = HWR[Rd]
Rt = SGPR[SRSCtl
Rd = Rt
Rd = Rt
(byte)Mem[Rs+offset] = Rt
if LLbit = 1
Rt = LLbit
Rd = SignExtend(Rs-7..0)
Rd = SignExtend(Rs-15..0)
(half)Mem[Rs+offset] = Rt
Rd = Rt << sa
Rd = Rt << Rs[4:0]
if (int)Rs < (int)Rt
else
if (int)Rs < (int)Immed
else
if (uns)Rs < (uns)Immed
else
if (uns)Rs < (uns)Immed
else
Rd = (int)Rt >> sa
Rd = (int)Rt >> Rs[4:0]
Rd = (uns)Rt >> sa
Rd = (uns)Rt >> Rs[4:0]
NOP
Rt = (int)Rs - (int)Rd
Rt = (uns)Rs - (uns)Rd
Mem[Rs+offset] = Rt
Mem[Rs+offset] = Rt
Mem[Rs+offset] = Rt
Trap to SW Debug Handler
Rd = 1
Rd = 0
Rt = 1
Rt = 0
Rt = 1
Rt = 0
Rd = 1
Rd = 0
mem[Rs+offset> = Rt
sa-1..0
Rs-1..0
 2009 Microchip Technology Inc.
Function
|| Rt
|| Rt
PSS
, Rd]
31..sa
31..Rs