PIC32MX795F512L-80I/PF Microchip Technology, PIC32MX795F512L-80I/PF Datasheet - Page 82

• Manufacturer Part Number: PIC32MX795F512L-80I/PF
• Description: IC MCU 32BIT 512KB FLASH 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX795F512L-80I/PF

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: MIPS32® M4K™
• Speed: 80MHz
• Connectivity: CAN, Ethernet, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Controller Family/series: PIC32
• Ram Memory Size: 128KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Interface: CAN, I2C, SPI, UART, USB
• No. Of Pwm Channels: 5
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: PIC32MX7xx
• Core: MIPS
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TABLE 4-22:
TABLE 4-23:
Legend:
Note
Legend:
Note
F400 NVMCON
F410
F420
F430 NVMDATA
F440
F000 OSCCON
F010
0000 WDTCON
F600
F610 RSWRST
NVMADDR
1:
1:
OSCTUN
NVMKEY
NVMSRC
2:
RCON
ADDR
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
Reset values are dependent on the DEVCFGx Configuration bits and the type of reset.
(1)
(1)
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
FLASH CONTROLLER REGISTER MAP
SYSTEM CONTROL REGISTER MAP
NVMWR NVMWREN NVMERR
31/15
31/15
ON
—
—
—
—
—
—
—
—
—
—
30/14
30/14
—
—
—
—
—
—
—
—
—
—
COSC<2:0>
29/13
29/13
—
—
—
—
—
—
—
—
—
PLLODIV<2:0>
LVDERR
28/12
28/12
—
—
—
—
—
—
—
—
—
LVDSTAT
27/11
27/11
—
—
—
—
—
—
—
—
—
—
(1,2)
26/10
26/10
—
—
—
—
—
—
—
—
—
—
RCDIV<2:0>
NOSC<2:0>
25/9
CM
25/9
—
—
—
—
—
—
—
—
—
NVMSRCADDR<31:0>
VREGS
NVMADDR<31:0>
24/8
NVMDATA<31:0>
NVMKEY<31:0>
24/8
—
—
—
—
—
—
—
—
—
Bits
Bits
CLKLOCK
EXTR
23/7
23/7
—
—
—
—
—
—
—
—
—
—
SOSCRDY
ULOCK
22/6
SWR
22/6
—
—
—
—
—
—
—
—
LOCK
21/5
21/5
—
—
—
—
—
—
—
—
—
SWDTPS<4:0>
SLPEN
WDTO
20/4
20/4
—
—
—
—
—
—
—
PBDIV<1:0>
SLEEP
19/3
19/3
CF
—
—
—
—
—
—
TUN<5:0>
UFRCEN
IDLE
18/2
18/2
—
—
—
—
—
—
NVMOP<3:0>
PLLMULT<2:0>
SOSCEN
17/1
17/1
BOR
—
—
—
—
—
—
—
WDTCLR 0000
OSWEN
SWRST
16/0
16/0
POR
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000