P87LPC760BDH,112 NXP Semiconductors, P87LPC760BDH,112 Datasheet - Page 16

• Manufacturer Part Number: P87LPC760BDH,112
• Description: IC 80C51 MCU 1K OTP 14-TSSOP
• Manufacturer: NXP Semiconductors
• Series: LPC700r

Specifications of P87LPC760BDH,112

• Program Memory Type: OTP
• Program Memory Size: 1KB (1K x 8)
• Package / Case: 14-TSSOP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, WDT
• Number Of I /o: 12
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Processor Series: P87LPC7x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C/UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: OM10063 - PROGRAMMER LPC700 P76XLCPOM10050 - EMULATOR LPC700 PDS76X
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-1015-5; 935271146112; P87LPC760BDH

Philips Semiconductors
Checking ATN and DRDY
When a program detects ATN = 1, it should next check DRDY. If
DRDY = 1, then if it receives the last bit, it should capture the data
from RDAT (in I2DAT or I2CON). Next, if the next bit is to be sent, it
should be written to I2DAT. One way or another, it should clear
DRDY and then return to monitoring ATN. Note that if any of ARL,
STR, or STP is set, clearing DRDY will not release SCL to high, so
that the I
ATN = 1, and DRDY = 0, it should go on to examine ARL, STR,
and STP.
ARL
STR
STP
MASTER
Writing I2CON
Typically, for each bit in an I
ATN = 1. Based on DRDY, ARL, STR, and STP, and on the current
2002 Mar 07
Low power, low price, low pin count (14 pin)
microcontroller with 1 kbyte OTP
2
C will not go on to the next bit. If a program detects
“Arbitration Loss” is 1 when transmit Active was set, but
this device lost arbitration to another transmitter.
Transmit Active is cleared when ARL is 1. There are
four separate cases in which ARL is set.
1. If the program sent a 1 or repeated start, but another
device sent a 0, or a stop, so that SDA is 0 at the rising
edge of SCL. (If the other device sent a stop, the
setting of ARL will be followed shortly by STP being
set.)
2. If the program sent a 1, but another device sent a
repeated start, and it drove SDA low before SCL
could be driven low. (This type of ARL is always
accompanied by STR = 1.)
3. In master mode, if the program sent a repeated start,
but another device sent a 1, and it drove SCL low
before this device could drive SDA low.
4. In master mode, if the program sent stop, but it could
not be sent because another device sent a 0.
“STaRt” is set to a 1 when an I
detected at a non-idle slave or at a master. (STR is not
set when an idle slave becomes active due to a start
bit; the slave has nothing useful to do until the rising
edge of SCL sets DRDY.)
“SToP” is set to 1 when an I
detected at a non-idle slave or at a master. (STP is not
set for a stop condition at an idle slave.)
“MASTER” is 1 if this device is currently a master on
the I
bus is not busy (i.e., if a start bit hasn’t been
received since reset or a “Timer I” time-out, or if a stop
has been received since the last start). MASTER is
cleared when ARL is set, or after the software writes
MASTRQ = 0 and then XSTP = 1.
2
C. MASTER is set when MASTRQ is 1 and the
2
C message, a service routine waits for
2
C stop condition is
2
C start condition is
13
CSTP
bit position in the message, it may then write I2CON with one or
more of the following bits, or it may read or write the I2DAT register.
CXA
Regarding Transmit Active
Transmit Active is set by writing the I2DAT register, or by writing
I2CON with XSTR = 1 or XSTP = 1. The I
the SDA line low when Transmit Active is set, and the ARL bit will
only be set to 1 when Transmit Active is set. Transmit Active is
cleared by reading the I2DAT register, or by writing I2CON with CXA
= 1. Transmit Active is automatically cleared when ARL is 1.
IDLE
CDR
CARL
CSTR
XSTR
XSTP
Writing a 1 to “Clear Xmit Active” clears the Transmit
Active state. (Reading the I2DAT register also does
this.)
Writing 1 to “IDLE” causes a slave’s I
ignore the I
MASTRQ is 1, then a stop condition will cause this
device to become a master).
Writing a 1 to “Clear Data Ready” clears DRDY.
(Reading or writing the I2DAT register also does this.)
Writing a 1 to “Clear Arbitration Loss” clears the ARL
bit.
Writing a 1 to “Clear STaRt” clears the STR bit.
Writing a 1 to “Clear SToP” clears the STP bit. Note that
if one or more of DRDY, ARL, STR, or STP is 1, the low
time of SCL is stretched until the service routine
responds by clearing them.
Writing 1s to “Xmit repeated STaRt” and CDR tells the
I
should only be at a master. Note that XSTR need not
and should not be used to send an “initial”
(non-repeated) start; it is sent automatically by the I
hardware. Writing XSTR = 1 includes the effect of
writing I2DAT with XDAT = 1; it sets Transmit Active
and releases SDA to high during the SCL low time.
After SCL goes high, the I
suitable minimum time and then drives SDA low to
make the start condition.
Writing 1s to “Xmit SToP” and CDR tells the I
hardware to send a stop condition. This should only be
done at a master. If there are no more messages to
initiate, the service routine should clear the MASTRQ
bit in I2CFG to 0 before writing XSTP with 1. Writing
XSTP = 1 includes the effect of writing I2DAT with
XDAT = 0; it sets Transmit Active and drives SDA low
during the SCL low time. After SCL goes high, the I
hardware waits for the suitable minimum time and then
releases SDA to high to make the stop condition.
2
C hardware to send a repeated start condition. This
2
C until the next start condition (but if
2
C hardware waits for the
2
C interface will only drive
P87LPC760
2
C hardware to
Preliminary data
2
C
2
2
C
C