ST7FLITEU09M6 STMicroelectronics, ST7FLITEU09M6 Datasheet - Page 53

MCU 8BIT SGL VOLT FLASH SO-8

ST7FLITEU09M6

Manufacturer Part Number
ST7FLITEU09M6
Description
MCU 8BIT SGL VOLT FLASH SO-8
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST7FLITEU09M6

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
5
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Processor Series
ST7FLITEUx
Core
ST7
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
ICC
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
5
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7FLITU0-D/RAIS, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 5 Channel
Cpu Family
ST7
Device Core Size
8b
Frequency (max)
8MHz
Total Internal Ram Size
128Byte
# I/os (max)
5
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3.3V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
8
Package Type
SO N
For Use With
497-5858 - EVAL BOARD PLAYBACK ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / Rohs Status
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ST7LITEU05 ST7LITEU09
9.4
9.4.1
Caution:
Active-halt and Halt modes
Active-Halt and Halt modes are the two lowest power consumption modes of the MCU. They
are both entered by executing the ‘Halt’ instruction. The decision to enter either in Active-
Halt or Halt mode is given by the LTCSR/ATCSR register status as shown in the following
table:
Table 16.
Active-halt mode
Active-halt mode is the lowest power consumption mode of the MCU with a real time clock
available. It is entered by executing the ‘Halt’ instruction when active halt mode is enabled.
The MCU can exit Active-halt mode on reception of a Lite Timer / AT Timer interrupt or a
Reset.
When entering Active-Halt mode, the I bit in the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Active-halt mode, only the main oscillator and the selected timer counter (LT/AT) are
running to keep a wake-up time base. All other peripherals are not clocked except those
which get their clock supply from another clock generator (such as external or auxiliary
oscillator).
As soon as Active-halt is enabled, executing a HALT instruction while the Watchdog is active
does not generate a Reset if the WDGHalt bit is reset.
This means that the device cannot spend more than a defined delay in this power saving
mode.
Figure 25. Active-halt timing overview
LTCSR TBIE
When exiting Active-halt mode by means of a Reset, a 256 or 512 CPU cycle delay
occurs. After the start up delay, the CPU resumes operation by fetching the reset vector
which woke it up (see
When exiting Active-Halt mode by means of an interrupt, the CPU immediately
resumes operation by servicing the interrupt vector which woke it up (see
bit
0
0
0
1
x
Enabling/disabling Active-halt and Halt modes
ATCSR OVFIE
bit
x
0
1
x
1
[Active Halt Enabled]
Figure
INSTRUCTION
RUN
HALT
ATCSRCK1 bit ATCSRCK0 bit
ACTIVE
26).
HALT
1
0
x
x
x
256 OR 512 CPU
CYCLE DELAY
INTERRUPT
RESET
OR
1)
VECTOR
0
1
1
x
x
FETCH
RUN
Active-Halt mode disabled
Active-Halt mode enabled
Power saving modes
Meaning
Figure
53/139
26).

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