ST7FLITEU09M6 STMicroelectronics, ST7FLITEU09M6 Datasheet - Page 55

• Manufacturer Part Number: ST7FLITEU09M6
• Description: MCU 8BIT SGL VOLT FLASH SO-8
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITEU09M6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: ST7FLITEUx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: ICC
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7FLITU0-D/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 128Byte
• # I/os (max): 5
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3.3V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SO N
• For Use With: 497-5858 - EVAL BOARD PLAYBACK ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -
• Lead Free Status / Rohs Status: Details

ST7LITEU05 ST7LITEU09
Figure 27. Halt timing overview
Figure 28. Halt mode flowchart
1. WDGHALT is an option bit. See option byte section for more details.
2. Peripheral clocked with an external clock source can still be active.
3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to
4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
5. The CPU clock must be switched to 1 MHz (RC/8) or AWU RC before entering Halt mode.
Halt mode recommendations
●
●
Table 10, “Interrupt mapping,” on page 44 for more details.
during the interrupt routine and cleared when the CC register is popped.
Make sure that an external event is available to wake up the microcontroller from Halt
mode.
When using an external interrupt to wake up the microcontroller, reinitialize the
corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT
[Active Halt disabled]
INSTRUCTION
RUN
N
HALT INSTRUCTION
(Active Halt disabled)
WATCHDOG
WDGHALT
HALT
RESET
1
INTERRUPT
HALT
Y
1)
CPU CYCLE
ENABLE
3)
INTERRUPT
256 OR 512
RESET
256 OR 512 CPU CLOCK
OR SERVICE INTERRUPT
0
FETCH RESET VECTOR
OR
OSCILLATOR
PERIPHERALS
CPU
OSCILLATOR
PERIPHERALS
CPU
OSCILLATOR
PERIPHERALS
CPU
I BIT
I BIT
I BITS
N
CYCLE DELAY
DELAY
RESET
WATCHDOG
Y
VECTOR
FETCH
DISABLE
2)
RUN
OFF
OFF
OFF
OFF
ON
ON
X
5)
ON
ON
ON
X
0
4)
4)
Power saving modes
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