Z8F012ASB020EG Zilog, Z8F012ASB020EG Datasheet - Page 190

• Manufacturer Part Number: Z8F012ASB020EG
• Description: IC ENCORE XP MCU FLASH 1K 8SOIC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F012ASB020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 16 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: Z8F012Ax
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z8F04A08100KITG, Z8F04A28100KITG, ZENETSC0100ZACG, ZENETSC0100ZACG, ZUSBOPTSC01ZACG, ZUSBSC00100ZAC, ZUSBSC00100ZACG
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4038; Z8F012ASB020EG

On-Chip Debugger Commands
PS022825-0908
Debug Command
Read OCD Revision
Reserved
Read OCD Status Register
Read Runtime Counter
Write OCD Control Register
Read OCD Control Register
Write Program Counter
Read Program Counter
Runtime Counter
Breakpoints in Flash Memory
The
byte in Flash memory. To implement a Breakpoint, write
address, overwriting the current instruction. To remove a Breakpoint, the corresponding
page of Flash memory must be erased and reprogrammed with the original data.
The On-Chip Debugger contains a 16-bit Runtime Counter. It counts system clock cycles
between Breakpoints. The counter starts counting when the On-Chip Debugger leaves
DEBUG mode and stops counting when it enters DEBUG mode again or when it reaches
the maximum count of
The host communicates to the on-chip debugger by sending OCD commands using the
DBG interface. During normal operation, only a subset of the OCD commands are avail-
able. In DEBUG mode, all OCD commands become available unless the user code and
control registers are protected by programming the Flash Read Protect Option bit (
The Flash Read Protect Option bit prevents the code in memory from being read out of the
Z8 Encore! XP F082A Series products. When this option is enabled, several of the OCD
commands are disabled.
commands. Each OCD command is described in further detail in the bulleted list follow-
ing this table.
device is not in DEBUG mode (normal operation) and those commands that are disabled
by programming the Flash Read Protect Option bit.
BRK
instruction is opcode
Table 106
Command
Byte
00H
01H
02H
03H
04H
05H
06H
07H
FFFFH
on page 184 also indicates those commands that operate when the
Table 106
NOT in DEBUG
.
Enabled when
00H
mode?
, which corresponds to the fully programmed state of a
on page 184 is a summary of the On-chip debugger
Yes
Yes
Yes
Yes
–
–
–
–
Flash Read Protect Option Bit
Cannot clear DBGMODE bit
Z8 Encore! XP
00H
to the required break
Disabled by
Product Specification
Disabled
Disabled
–
–
–
–
–
®
On-Chip Debugger
F082A Series
FRP
).
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