Z8F012ASB020EG Zilog, Z8F012ASB020EG Datasheet - Page 218

• Manufacturer Part Number: Z8F012ASB020EG
• Description: IC ENCORE XP MCU FLASH 1K 8SOIC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F012ASB020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 16 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: Z8F012Ax
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z8F04A08100KITG, Z8F04A28100KITG, ZENETSC0100ZACG, ZENETSC0100ZACG, ZUSBOPTSC01ZACG, ZUSBSC00100ZAC, ZUSBSC00100ZACG
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4038; Z8F012ASB020EG

eZ8 CPU Instruction Summary
.
Table 124. eZ8 CPU Instruction Summary
PS022825-0908
Assembly
Mnemonic
ADC dst, src
ADCX dst, src
ADD dst, src
ADDX dst, src
Flags Notation:
Table 123. Rotate and Shift Instructions (Continued)
Table 124
modes employed by the instruction, the effect upon the Flags register, the number of CPU
clock cycles required for the instruction fetch, and the number of CPU clock cycles
required for the instruction execution.
Mnemonic Operands
SRA
SRL
SWAP
Symbolic
Operation
dst ← dst + src + C
dst ← dst + src + C
dst ← dst + src
dst ← dst + src
* = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
summarizes the eZ8 CPU instructions. The table identifies the addressing
dst
dst
dst
Address Mode
dst
ER
ER
ER
ER
IR
IR
Instruction
Shift Right Arithmetic
Shift Right Logical
Swap Nibbles
R
R
R
R
R
R
r
r
r
r
src
ER
ER
IM
IM
IM
IM
IM
IM
IR
IR
R
R
Ir
Ir
r
r
Opcode(s)
(Hex)
12
13
14
15
16
17
18
19
02
03
04
05
06
07
08
09
0 = Reset to 0
1 = Set to 1
C
*
*
*
*
Z8 Encore! XP
Z
*
*
*
*
Flags
S V
*
*
*
*
Product Specification
*
*
*
*
eZ8 CPU Instruction Set
D
0
0
0
0
®
H
*
*
*
*
F082A Series
Cycles
Fetch
2
2
3
3
3
3
4
4
2
2
3
3
3
3
4
4
Cycles
Instr.
3
4
3
4
3
4
3
3
3
4
3
4
3
4
3
3
207