Z8F012ASB020EG Zilog, Z8F012ASB020EG Datasheet - Page 76

• Manufacturer Part Number: Z8F012ASB020EG
• Description: IC ENCORE XP MCU FLASH 1K 8SOIC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F012ASB020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 16 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 8-SOIC (3.9mm Width)
• Processor Series: Z8F012Ax
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z8F04A08100KITG, Z8F04A28100KITG, ZENETSC0100ZACG, ZENETSC0100ZACG, ZUSBOPTSC01ZACG, ZUSBSC00100ZAC, ZUSBSC00100ZACG
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4038; Z8F012ASB020EG

Table 43. IRQ2 Enable High Bit Register (IRQ2ENH)
Table 44. IRQ2 Enable Low Bit Register (IRQ2ENL)
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS022825-0908
IRQ2 Enable High and Low Bit Registers
7
R/W
R/W
7
0
0
Table 42
registers
Interrupt Request 2 register.
Table 42. IRQ2 Enable and Priority Encoding
Reserved—Must be 0.
C3ENH—Port C3 Interrupt Request Enable High Bit
C2ENH—Port C2 Interrupt Request Enable High Bit
C1ENH—Port C1 Interrupt Request Enable High Bit
C0ENH—Port C0 Interrupt Request Enable High Bit
IRQ2ENH[x] IRQ2ENL[x] Priority
0
0
1
1
where x indicates the register bits from 0–7.
6
(Table 43
describes the priority control for IRQ2. The IRQ2 Enable High and Low Bit
R/W
R/W
6
0
0
Reserved
Reserved
0
1
0
1
5
and
R/W
R/W
Table
5
0
0
44) form a priority encoded enabling for interrupts in the
Disabled
Level 1
Level 2
Level 3
4
R/W
R/W
4
0
0
FC7H
FC8H
3
C3ENH
C3ENL
R/W
R/W
Description
Disabled
Low
Medium
High
3
0
0
2
Z8 Encore! XP
C2ENH
C2ENL
R/W
R/W
2
0
0
Product Specification
1
C1ENH
C1ENL
R/W
R/W
1
0
0
®
Interrupt Controller
F082A Series
0
C0ENH
C0ENL
R/W
R/W
0
0
0
65