ST72F623F2M1TR STMicroelectronics, ST72F623F2M1TR Datasheet - Page 53

• Manufacturer Part Number: ST72F623F2M1TR
• Description: IC MCU 8BIT 8K FLASH 20-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F623F2M1TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 11
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST72F6x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 11
• Number Of Timers: 2
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 3 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.3 TIMEBASE UNIT (TBU)
10.3.1 Introduction
The Timebase unit (TBU) can be used to generate
periodic interrupts.
10.3.2 Main Features
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10.3.3 Functional Description
The TBU operates as a free-running upcounter.
When the TCEN bit in the TBUCSR register is set
by software, counting starts at the current value of
the TBUCV register. The TBUCV register is incre-
mented at the clock rate output from the prescaler
selected by programming the PR[2:0] bits in the
TBUCSR register.
When the counter rolls over from FFh to 00h, the
OVF bit is set and an interrupt request is generat-
ed if ITE is set.
The user can write a value at any time in the
TBUCV register.
Figure 38. TBU Block Diagram
8-bit upcounter
Programmable prescaler
Period between interrupts: max. 8.1ms (at 8
MHz f
Maskable interrupt
Cascadable with PWM/ART TImer
TBU
f
CPU
TBU PRESCALER
CPU
)
1
0
TBU 8-BIT UPCOUNTER (TBUCV REGISTER)
MSB
0
CAS
OVF
ITE
TBUCSR REGISTER
TCEN
ART TIMER CARRY BIT
PR2
Doc ID 6996 Rev 5
PR1 PR0
INTERRUPT REQUEST
If the cascading option is selected (CAS bit=1 in
the TBUCSR register), the TBU and the ART TIm-
er counters act together as a 16-bit counter. In this
case, the TBUCV register is the high order byte,
the ART counter (ARTCAR register) is the low or-
der byte. Counting is clocked by the ART timer
clock (Refer to the description of the ART Timer
ARTCSR register).
10.3.4 Programming Example
In this example, timer is required to generate an in-
terrupt after a delay of 1 ms.
Assuming that f
sion factor of 256 will be programmed using the
PR[2:0] bits in the TBUCSR register, 1 ms = 32
TBU timer ticks.
In this case, the initial value to be loaded in the
TBUCV must be (256-32) = 224 (E0h).
ld A, E0h
ld TBUCV, A
ld A 1Fh
ld TBUCSR, A ; Prescaler factor = 256,
LSB
MSB
ART PWM TIMER 8-BIT COUNTER
CPU
; Initialize counter value
;
; interrupt enable,
; TBU enable
is 8 MHz and a prescaler divi-
ST7262xxx
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LSB