ST72F623F2M1TR STMicroelectronics, ST72F623F2M1TR Datasheet - Page 54

• Manufacturer Part Number: ST72F623F2M1TR
• Description: IC MCU 8BIT 8K FLASH 20-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F623F2M1TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 11
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST72F6x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 11
• Number Of Timers: 2
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 3 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST7262xxx
TIMEBASE UNIT (Cont’d)
10.3.5 Low Power Modes
10.3.6 Interrupts
Note: The OVF interrupt event is connected to an
interrupt vector (see Interrupts chapter).
It generates an interrupt if the ITE bit is set in the
TBUCSR register and the I-bit in the CC register is
reset (RIM instruction).
10.3.7 Register Description
TBU COUNTER VALUE REGISTER (TBUCV)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = CV[7:0] Counter Value
This register contains the 8-bit counter value
which can be read and written anytime by soft-
ware. It is continuously incremented by hardware if
TCEN=1.
TBU CONTROL/STATUS REGISTER (TBUCSR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = Reserved. Forced by hardware to 0.
54/139
Mode
WAIT
HALT
Counter Over-
flow Event
CV7
7
0
7
Interrupt
Event
CAS OVF
CV6
Description
No effect on TBU
TBU halted.
CV5
Event
Flag
OVF
ITE TCEN
CV4
Control
Enable
ITE
Bit
CV3
PR2
CV2
from
Wait
Exit
Yes
PR1
CV1
from
Halt
Exit
No
CV0
PR0
0
0
Doc ID 6996 Rev 5
Bit 6 = CAS Cascading Enable
This bit is set and cleared by software. It is used to
cascade the TBU and the PWM/ART timers.
0: Cascading disabled
1: Cascading enabled
Bit 5 = OVF Overflow Flag
This bit is set only by hardware, when the counter
value rolls over from FFh to 00h. It is cleared by
software reading the TBUCSR register. Writing to
this bit does not change the bit value.
0: No overflow
1: Counter overflow
Bit 4 = ITE Interrupt enabled.
This bit is set and cleared by software.
0: Overflow interrupt disabled
1: Overflow interrupt enabled. An interrupt request
Bit 3 = TCEN TBU Enable.
This bit is set and cleared by software.
0: TBU counter is frozen and the prescaler is reset.
1: TBU counter and prescaler running.
Bit 2:0 = PR[2:0] Prescaler Selection
These bits are set and cleared by software to se-
lect the prescaling factor.
PR2 PR1 PR0
is generated when OVF=1.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Prescaler Division Factor
128
256
16
32
64
2
4
8