ST72F623F2M1TR STMicroelectronics, ST72F623F2M1TR Datasheet - Page 60

• Manufacturer Part Number: ST72F623F2M1TR
• Description: IC MCU 8BIT 8K FLASH 20-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F623F2M1TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 11
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST72F6x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 11
• Number Of Timers: 2
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 3 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST7262xxx
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.4 Clock Phase and Clock Polarity
Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits (See
Figure
Note: The idle state of SCK must correspond to
the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if
CPOL=0).
The combination of the CPOL clock polarity and
CPHA (clock phase) bits selects the data capture
clock edge
Figure 43. Data Clock Timing Diagram
60/139
(from slave)
(from slave)
43).
(to slave)
(to slave)
(from master)
(from master)
MISO
MOSI
CAPTURE STROBE
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
MOSI
SS
CAPTURE STROBE
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
MSBit
MSBit
MSBit
MSBit
Bit 6
Bit 6
Bit 6
Bit 6
Bit 5
Bit 5
Bit 5
Bit 5
CPHA =0
CPHA =1
Bit 4
Bit 4
Bit 4
Bit 4
Doc ID 6996 Rev 5
Figure
combinations of the CPHA and CPOL bits. The di-
agram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
Bit3
Bit3
Bit3
Bit3
43, shows an SPI transfer with the four
Bit 2
Bit 2
Bit 2
Bit 2
Bit 1
Bit 1
Bit 1
Bit 1
LSBit
LSBit
LSBit
LSBit