ST72F561J4T6 STMicroelectronics, ST72F561J4T6 Datasheet - Page 136

• Manufacturer Part Number: ST72F561J4T6
• Description: IC MCU 8BIT 16K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F561J4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: ST72F5x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: 497-8374 - BOARD DEVELOPMENT FOR ST72F561
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
EXTENDED RECEIVE PRESCALER DIVISION
REGISTER (SCIERPR)
Read/Write
Reset Value: 0000 0000 (00 h)
Bits 7:0 = ERPR[7:0] 8-bit Extended Receive
Prescaler Register
The extended Baud Rate Generator is activated
when a value other than 00h is stored in this regis-
ter. The clock frequency from the 16 divider (see
Figure
SCIERPR register (in the range 1 to 255).
The extended baud rate generator is not active af-
ter a reset.
136/265
ERPR
7
7
ERPR
3) is divided by the binary factor set in the
6
ERPR
5
ERPR
4
ERPR
3
ERPR
2
ERPR
1
ERPR
0
0
EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (SCIETPR)
Read/Write
Reset Value:0000 0000 (00 h)
Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit
Prescaler Register
The extended Baud Rate Generator is activated
when a value other than 00h is stored in this regis-
ter. The clock frequency from the 16 divider (see
Figure
SCIETPR register (in the range 1 to 255).
The extended baud rate generator is not active af-
ter a reset.
Note: In LIN slave mode, the Conventional and
Extended Baud Rate Generators are disabled.
ETPR
7
7
ETPR
3) is divided by the binary factor set in the
6
ETPR
5
ETPR
4
ETPR
3
ETPR
2
ETPR
1
ETPR
0
0