ST72F561J4T6 STMicroelectronics, ST72F561J4T6 Datasheet - Page 60

• Manufacturer Part Number: ST72F561J4T6
• Description: IC MCU 8BIT 16K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F561J4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: ST72F5x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: 497-8374 - BOARD DEVELOPMENT FOR ST72F561
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST72561
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)
10.2.4 Low Power Modes
10.2.5 Interrupts
The MCC/RTC interrupt event generates an inter-
rupt if the OIE bit of the MCCSR register is set and
the interrupt mask in the CC register is not active
(RIM instruction).
Note:
The MCC/RTC interrupt wakes up the MCU from
ACTIVE HALT mode, not from HALT or AWUF
HALT mode.
10.2.6 Register Description
MCC CONTROL/STATUS REGISTER (MCCSR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7 = MCO Main clock out selection
This bit enables the MCO alternate function on the
corresponding I/O port. It is set and cleared by
software.
0: MCO alternate function disabled (I/O pin free for
1: MCO alternate function enabled (f
60/265
MCO CP1
WAIT
ACTIVE HALT
HALT
and
AWUF HALT
Time base overflow
event
general-purpose I/O)
port)
Interrupt Event
7
Mode
CP0
No effect on MCC/RTC peripheral.
MCC/RTC interrupt cause the device to
exit from WAIT mode.
No effect on MCC/RTC counter (OIE bit
is set), the registers are frozen.
MCC/RTC interrupt cause the device to
exit from ACTIVE HALT mode.
MCC/RTC counter and registers are fro-
zen.
MCC/RTC operation resumes when the
MCU is woken up by an interrupt with
“exit from HALT” capability.
SMS
Event
Flag
OIF
TB1
Description
Control
Enable
OIE
Bit
TB0
from
Wait
Exit
Yes
OSC2
OIE
on I/O
from
No
Exit
Halt
OIF
0
1)
Bits 6:5 = CP[1:0] CPU clock prescaler
These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the SMS bit. These
two bits are set and cleared by software
Bit 4 = SMS Slow mode select
This bit is set and cleared by software.
0: Normal mode. f
1: Slow mode. f
See
"MAIN CLOCK CONTROLLER WITH REAL TIME
CLOCK MCC/RTC"
Bits 3:2 = TB[1:0] Time base control
These bits select the programmable divider time
base. They are set and cleared by software.
A modification of the time base is taken into ac-
count at the end of the current period (previously
set) to avoid an unwanted time shift. This allows to
use this time base as a real time clock.
Bit 1 = OIE Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt can be used to exit from ACTIVE
HALT mode.
When this bit is set, calling the ST7 software HALT
instruction enters the ACTIVE HALT power saving
mode
Prescaler
Counter
200000
16000
32000
80000
Section 8.2 "SLOW MODE"
f
CPU
.
in SLOW mode
f
f
f
OSC2
f
f
OSC2
OSC2
OSC2
OSC2
20ms
50ms
/ 16
CPU
4ms
8ms
/ 8
/ 2
/ 4
=4 MHz f
CPU
Time Base
is given by CP1, CP0
for more details.
=
f
OSC2
OSC2
10ms
25ms
2ms
4ms
=8 MHz
CP1
and
0
0
1
1
Section 10.2
TB1
0
0
1
1
CP0
0
1
0
1
TB0
0
1
0
1