ST72F561J4T6 STMicroelectronics, ST72F561J4T6 Datasheet - Page 189

• Manufacturer Part Number: ST72F561J4T6
• Description: IC MCU 8BIT 16K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F561J4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: ST72F5x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: 497-8374 - BOARD DEVELOPMENT FOR ST72F561
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

beCAN CONTROLLER (Cont’d)
In the worst case configuration, if the CAN cell
speed is set to the maximum baud rate, one bit
time is 8 CPU cycle. In this case the minimum time
between the end of the acknowledge and the criti-
cal period is 52 CPU cycles (48 for the 6 bit times
+ 4 for the (PROP SEG + T
previous code timing, we need less than 15 cycles
from the time we see the dominant state to the
time we perform the FIFO release (one full loop +
the actual release) therefore the application will
never release the FIFO at the critical time when
this workaround is implemented.
Timing analysis
- Time spent in the workaround
Inside a CAN frame, the longest period that the Rx
pin stays in recessive state is 5 bits. At the end of
the frame, the time between the acknowledge
dominant bit and the end of reception (signaled by
REC bit status) is 8t
time
8t
8t
At low speed, this time could represent a long de-
lay for the application, therefore it makes sense to
evaluate how frequently this delay occurs.
Figure 111. Critical Window Timing Diagram
Figure 112. Reception of a Sequence of Frames
CANbit
CANbit
FMP
BUS
CPU
+t
+25t
spent
loop
CPU
+t
test
.
t
+t
CAN frame
in
CANbit
release
Acknowledge: last
dominant bit in the frame
0
the
, therefore the maximum
Seg 1
1
in
Time to test RX pin and to
release the FIFO 4.5µs@4 MHz Time between the end of the
workaround
). According to the
this
case
CAN Frame
t
IT disable
t
CAN frame
is:
or
1
In order to reach the critical FMP = 2, the CAN
node needs to receive two messages without serv-
icing them. Then in order to reach the critical win-
dow, the cell has to receive a third one and the ap-
plication has to release the mailbox at the same
time, at the end of the reception.
In the application, messages are not processed
only if either the interrupt are disabled or higher
level interrupts are being serviced.
Therefore if:
t
the application will never wait in the workaround
t
interrupts with a level strictly higher than the CAN
interrupt level
t
disables the CAN interrupt (or all interrupts)
t
beginning of the CAN interrupt and the actual loca-
tion of the workaround
t
IT higher level
IT higher level
IT disable
IT CAN
CAN frame
2
acknowledge and the critical windows
- 6 full CAN bit times + time to the sample point
approx. 13µs @ 500 Kbaud
: This is the maximum duration between the
Critical window: the received
message is placed in the FIFO
: This is the longest time the application
t
: This is minimum CAN frame duration
IT higher level
+ t
: This the sum of the duration of all the
IT disable
t
CAN frame
+ t
IT CAN
2
t
IT CAN
A release is not
allowed at this time
< 2 x t
3
CAN frame
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