ST10F272M-4T3 STMicroelectronics, ST10F272M-4T3 Datasheet - Page 167

• Manufacturer Part Number: ST10F272M-4T3
• Description: MCU 16BIT 256K FLASH 144-LQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F272M-4T3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Processor Series: ST10F27x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F272M
Figure 60. External bus arbitration (regaining the bus)
1. This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-
2. The next ST10F272M driven bus cycle may start here.
24.8.20
24.8.20.1 Master mode
V
Table 74.
t
t
t
t
t
t
t
Symbol
300
301
302
303
304
305
306
DD
sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the ST10F272M
requesting the bus.
= 5 V ±10 %, V
CC SSC clock cycle time
CC SSC clock high time
CC SSC clock low time
CC SSC clock rise time
CC SSC clock fall time
CC Write data valid after shift edge
CC Write data hold after shift edge
High-speed synchronous serial interface (SSC) timing
SSC master mode timings
CSx
(on P6.x)
Other
signals
CLKOUT
BREQ
HLDA
HOLD
SS
Parameter
= 0 V, T
(2)
A
= -40 to +125 °C, C
t
62
(3)
t
61
(1)
t
62
(<SSCBR> = 0002h)
Maximum baudrate
Min
150
63
63
@ f
-2
–
–
–
6.6 Mbaud
CPU
L
t
62
= 50 pF
= 40 MHz
t
t
63
67
(2)
(1)
Max
150
10
10
15
–
–
–
t
65
(<SSCBR> = 0001h - FFFFh)
t
t
300
300
8TCL
Min
Variable baudrate
/2 - 12
/2 - 12
-2
–
–
–
Electrical characteristics
262144 TCL
Max
10
10
15
–
–
–
167/176
Unit
ns
ns
ns
ns
ns
ns
ns