MC9S08AC16CFGE Freescale Semiconductor, MC9S08AC16CFGE Datasheet - Page 162

• Manufacturer Part Number: MC9S08AC16CFGE
• Description: IC MCU 8BIT 16K FLASH 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08AC16CFGE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Package: 44LQFP
• Family Name: HCS08
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 34
• Interface Type: I2C/SCI/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Processor Series: S08AC
• Core: HCS08
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 40 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08AC60E, DEMOACEX, DEMOACKIT, DCF51AC256, DC9S08AC128, DC9S08AC16, DC9S08AC60, DEMO51AC256KIT
• Minimum Operating Temperature: - 40 C
• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Total Internal Ram Size: 1KB
• # I/os (max): 34
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 10 Timer/PWM (S08TPMV3)
162
1
2
3
4
5
6
7
In Edge-Aligned PWM mode when (CLKSB:CLKSA not = 00),
writes to TPMxCnVH:L registers
In Center-Aligned PWM mode when (CLKSB:CLKSA not =
00), writes to TPMxCnVH:L registers
Center-Aligned PWM
When TPMxCnVH:L = TPMxMODH:L
When TPMxCnVH:L = (TPMxMODH:L - 1)
TPMxCnVH:L is changed from 0x0000 to a non-zero value
TPMxCnVH:L is changed from a non-zero value to 0x0000
Write to TPMxMODH:L registers in BDM mode
In BDM mode, a write to TPMxSC register
For more information, refer to
For more information, refer to
For more information, refer to
For more information, refer to
For more information, refer to
For more information, refer to
For more information, refer to
Table 10-1. TPMV2 and TPMV3 Porting Considerations (continued)
Action
Section 10.5.2, “TPM-Counter Registers
Section 10.5.5, “TPM Channel Value Registers
Section 10.6.2.1, “Input Capture
Section 10.6.2.4, “Center-Aligned PWM
Section 10.6.2.4, “Center-Aligned PWM
Section 10.6.2.4, “Center-Aligned PWM
Section 10.6.2.4, “Center-Aligned PWM
4
5
MC9S08AC16 Series Data Sheet, Rev. 8
6
7
8
Update the TPMxCnVH:L
registers with the value of
their write buffer after both
bytes were written and when
the TPM counter changes
from (TPMxMODH:L - 1) to
(TPMxMODH:L).
Note: If the TPM counter is a
free-running counter, then
this update is made when the
TPM counter changes from
$FFFE to $FFFF.
Update the TPMxCnVH:L
registers with the value of
their write buffer after both
bytes are written and when
the TPM counter changes
from (TPMxMODH:L - 1) to
(TPMxMODH:L).
Note: If the TPM counter is a
free-running counter, then
this update is made when the
TPM counter changes from
$FFFE to $FFFF.
Produces 100% duty cycle.
Produces a near 100% duty
cycle.
Waits for the start of a new
PWM period to begin using
the new duty cycle setting.
Finishes the current PWM
period using the old duty
cycle setting.
Clears the write coherency
mechanism of TPMxMODH:L
registers.
Mode.”
Mode.”
Mode.” [SE110-TPM case 1]
Mode.” [SE110-TPM case 2]
Mode.” [SE110-TPM case 3 and 5]
(TPMxCNTH:TPMxCNTL).” [SE110-TPM case 7]
TPMV3
(TPMxCnVH:TPMxCnVL).”
Update after both bytes are
written and when the TPM
counter changes from
TPMxMODH:L to $0000.
Update after both bytes are
written and when the TPM
counter changes from
TPMxMODH:L to
(TPMxMODH:L - 1).
Produces 0% duty cycle.
Produces 0% duty cycle.
Changes the channel output at
the middle of the current PWM
period (when the count
reaches 0x0000).
Finishes the current PWM
period using the new duty cycle
setting.
Does not clear the write
coherency mechanism.
Freescale Semiconductor
TPMV2