MC9S08AC16CFGE Freescale Semiconductor, MC9S08AC16CFGE Datasheet - Page 235

IC MCU 8BIT 16K FLASH 44-LQFP

MC9S08AC16CFGE

Manufacturer Part Number
MC9S08AC16CFGE
Description
IC MCU 8BIT 16K FLASH 44-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet

Specifications of MC9S08AC16CFGE

Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-LQFP
Package
44LQFP
Family Name
HCS08
Maximum Speed
40 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
34
Interface Type
I2C/SCI/SPI
On-chip Adc
8-chx10-bit
Number Of Timers
8
Processor Series
S08AC
Core
HCS08
Data Ram Size
1 KB
Maximum Clock Frequency
40 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08AC60E, DEMOACEX, DEMOACKIT, DCF51AC256, DC9S08AC128, DC9S08AC16, DC9S08AC60, DEMO51AC256KIT
Minimum Operating Temperature
- 40 C
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
40MHz
Total Internal Ram Size
1KB
# I/os (max)
34
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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13.4
This section provides a complete functional description of the IIC module.
13.4.1
The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices
connected to it must have open drain or open collector outputs. A logic AND function is exercised on both
lines with external pull-up resistors. The value of these resistors is system dependent.
Normally, a standard communication is composed of four parts:
The stop signal should not be confused with the CPU stop instruction. The IIC bus system communication
is described briefly in the following sections and illustrated in
13.4.1.1
When the bus is free, no master device is engaging the bus (SCL and SDA lines are at logical high), a
master may initiate communication by sending a start signal. As shown in
defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new
data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle
states.
Freescale Semiconductor
SCL
SDA
SCL
SDA
Start signal
Slave address transmission
Data transfer
Stop signal
Functional Description
Signal
Signal
Start
Start
IIC Protocol
Start Signal
msb
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
msb
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
1
1
2
2
Calling Address
Calling Address
3
3
4
4
5
5
Figure 13-9. IIC Bus Transmission Signals
MC9S08AC16 Series Data Sheet, Rev. 8
6
6
7
7
Read/
Read/
Write
Write
lsb
lsb
8
8
Ack
Ack
Bit
9
Bit
9
XX
Repeated
XXX
Signal
Start
msb
msb
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
D7
1
1
Figure
D6
2
2
New Calling Address
D5
3
3
13-9.
Data Byte
D4
4
4
D3
Figure
5
5
Inter-Integrated Circuit (S08IICV2)
D2
6
6
13-9, a start signal is
D1
7
7
Read/
Write
lsb
lsb
D0
8
8
Ack
No
Bit
Ack
No
9
Bit
9
Signal
Stop
Signal
Stop
235

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