MC9S12XEQ384MAG Freescale Semiconductor, MC9S12XEQ384MAG Datasheet - Page 169

• Manufacturer Part Number: MC9S12XEQ384MAG
• Description: MCU 16BIT 384K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEQ384MAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 24 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• Package: 144LQFP
• Family Name: HCS12X
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 1.8|2.8|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime.
1. Read: Anytime.
2.3.87
2.3.88
Freescale Semiconductor
Address 0x036A
Address 0x036B
Write: Anytime.
Write: Anytime.
DDRR
Field
Reset
Reset
7-0
W
W
R
R
Port R data direction—
This register controls the data direction of pins 7 through 0.
The TIM forces the I/O state to be an output for each timer port associated with an enabled output compare. In this
case the data direction bits will not change.
The data direction bits revert to controlling the I/O direction of a pin when the associated timer output compare is
disabled.
The timer Input Capture always monitors the state of the pin.
1 Associated pin is configured as output.
0 Associated pin is configured as high-impedance input.
DDRR7
RDRR7
Port R Data Direction Register (DDRR)
Port R Reduced Drive Register (RDRR)
0
0
7
7
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTR or PTIR registers, when changing the
DDRR register.
DDRR6
RDRR6
0
0
6
6
Figure 2-86. Port R Reduced Drive Register (RDRR)
Figure 2-85. Port R Data Direction Register (DDRR)
Table 2-83. DDRR Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
DDRR5
RDRR5
0
0
5
5
DDRR4
RDRR4
NOTE
0
0
4
4
Description
DDRR3
RDRR3
3
0
3
0
Chapter 2 Port Integration Module (S12XEPIMV1)
DDRR2
RDRR2
0
0
2
2
Access: User read/write
Access: User read/write
DDRR1
RDRR1
0
0
1
1
DDRR0
RDRR0
0
0
0
0
169
(1)
(1)