MC908MR32CFUE Freescale Semiconductor, MC908MR32CFUE Datasheet - Page 105

• Manufacturer Part Number: MC908MR32CFUE
• Description: IC MCU 8MHZ 32K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908MR32CFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 44
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08MR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 6
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.3.2 Data Direction Register B
Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a
logic 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the
output buffer.
DDRB[7:0] — Data Direction Register B Bits
Figure 10-7
When bit DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When bit DDRBx is a
logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
Freescale Semiconductor
These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins
as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect input.
DDRB Bit
shows the port B I/O logic.
Address:
0
1
Reset:
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Read:
Write:
READ DDRB ($0005)
WRITE DDRB ($0005)
WRITE PTB ($0001)
READ PTB ($0001)
DDRB7
$0005
Bit 7
PTB Bit
0
X
X
(1)
Figure 10-6. Data Direction Register B (DDRB)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
DDRB6
6
0
I/O Pin Mode
Input, Hi-Z
Table 10-2. Port B Pin Functions
RESET
Figure 10-7. Port B I/O Circuit
Output
DDRB5
5
0
(2)
Table 10-2
DDRB4
NOTE
DDRBx
PTBx
4
0
Accesses to DDRB
Read/Write
DDRB[7:0]
DDRB[7:0]
DDRB3
summarizes the operation of the port B pins.
3
0
DDRB2
2
0
PTB[7:0]
Read
DDRB1
Pin
Accesses to PTB
1
0
DDRB0
Bit 0
PTB[7:0]
PTB[7:0]
0
PTBx
Write
(3)
Port B
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