MC908MR32CFUE Freescale Semiconductor, MC908MR32CFUE Datasheet - Page 37

IC MCU 8MHZ 32K FLASH 64-QFP

MC908MR32CFUE

Manufacturer Part Number
MC908MR32CFUE
Description
IC MCU 8MHZ 32K FLASH 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908MR32CFUE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
44
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Processor Series
HC08MR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SCI/SPI
Maximum Clock Frequency
8.2 MHz
Number Of Programmable I/os
44
Number Of Timers
6
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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2.6 Monitor ROM
The 240 bytes at addresses $FE10–$FEFF are reserved ROM addresses that contain the instructions for
the monitor functions. See
2.7 Random-Access Memory (RAM)
Addresses $0060–$035F are RAM locations. The location of the stack RAM is programmable. The 16-bit
stack pointer allows the stack to be anywhere in the 64-Kbyte memory space.
Within page zero are 160 bytes of RAM. Because the location of the stack RAM is programmable, all page
zero RAM locations can be used for input/output (I/O) control and user data or code. When the stack
pointer is moved from its reset location at $00FF, direct addressing mode instructions can access
efficiently all page zero RAM locations. Page zero RAM, therefore, provides ideal locations for frequently
accessed global variables.
Before processing an interrupt, the central processor unit (CPU) uses five bytes of the stack to save the
contents of the CPU registers.
Freescale Semiconductor
For correct operation, the stack pointer must point only to RAM locations.
For M68HC05 and M1468HC05 compatibility, the H register is not stacked.
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
18.3 Monitor ROM
Table 2-1. Vector Addresses (Continued)
Address
$FFEE
$FFEF
$FFFB
$FFFC
$FFFD
$FFFE
$FFFF
$FFF0
$FFF1
$FFF2
$FFF3
$FFF4
$FFF5
$FFF6
$FFF7
$FFF8
$FFF9
$FFFA
(MON).
PWMMC vector (high)
PWMMC vector (low)
FAULT 4 (high)
FAULT 4 (low)
FAULT 3 (high)
FAULT 3 (low)
FAULT 2 (high)
FAULT 2 (low)
FAULT 1 (high)
FAULT 1 (low)
PLL vector (high)
PLL vector (low)
IRQ vector (high)
IRQ vector (low)
SWI vector (high)
SWI vector (low)
Reset vector (high)
Reset vector (low)
NOTE
NOTE
Vector
Monitor ROM
37

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