MC9S12C64CFUE Freescale Semiconductor, MC9S12C64CFUE Datasheet - Page 274

• Manufacturer Part Number: MC9S12C64CFUE
• Description: IC MCU 64K FLASH 4K RAM 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C64CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12C
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912C32EE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 2.5|5 V
• Height: 2.4 mm
• Length: 14 mm
• Supply Voltage (max): 2.75 V, 5.5 V
• Supply Voltage (min): 2.35 V, 2.97 V
• Width: 14 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
9.4.8
The RTI can be stopped by setting the associated rate select bits to 0.
The COP can be stopped by setting the associated rate select bits to 0.
9.4.9
The WAI instruction puts the MCU in a low power consumption stand-by mode depending on setting of
the individual bits in the CLKSEL register. All individual wait mode configuration bits can be superposed.
This provides enhanced granularity in reducing the level of power consumption during wait mode.
10
After executing the WAI instruction the core requests the CRG to switch MCU into wait mode. The CRG
then checks whether the PLLWAI, CWAI and SYSWAI bits are asserted (see
the configuration the CRG switches the system and core clocks to OSCCLK by clearing the PLLSEL bit,
disables the PLL, disables the core clocks and finally disables the remaining system clocks. As soon as all
clocks are switched off wait mode is active.
274
lists the individual configuration bits and the parts of the MCU that are affected in wait mode.
Low-Power Operation in Run Mode
Low-Power Operation in Wait Mode
1. Refer to oscillator block description for availability of a reduced oscillator amplitude.
In order to detect a potential clock loss, the CME bit should be always
enabled (CME=1).
If CME bit is disabled and the MCU is configured to run on PLL clock
(PLLCLK), a loss of external clock (OSCCLK) will not be detected and will
cause the system clock to drift towards the VCO’s minimum frequency
f
ramps up to its PLL target frequency. If the MCU is running on external
clock any loss of clock will cause the system to go static.
SCM
Oscillator
System
Core
COP
PLL
RTI
. As soon as the external clock is available again the system clock
Table 9-10. MCU Configuration During Wait Mode
PLLWAI
stopped
—
—
—
—
—
MC9S12C-Family / MC9S12GC-Family
stopped
CWAI
—
—
—
—
—
Rev 01.24
NOTE
SYSWAI
stopped
stopped
—
—
—
—
stopped
RTIWAI
—
—
—
—
—
COPWAI
stopped
—
—
—
—
—
Figure
reduced
ROAWAI
9-23). Depending on
Freescale Semiconductor
—
—
—
—
—
(1)
Table 9-