R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet - Page 125

• Manufacturer Part Number: R4F24268NVFQV
• Description: MCU 256K FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24268NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2426, H8S/2426R, H8S/2424 Group
4.1
As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, illegal
instruction, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or
more exceptions occur simultaneously, they are accepted and processed in order of priority.
Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt
control mode. For details on the interrupt control mode, refer to section 5, Interrupt Controller.
Table 4.1
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
Priority
High
Low
2. Not available in this LSI.
3. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
4. Trap instruction exception handling requests are accepted at all times in program
Exception Handling Types and Priority
executed after execution of an RTE instruction.
instruction execution, or on completion of reset exception handling.
execution state.
Exception Type
Reset
Illegal instruction
Trace*
Direct transition*
Interrupt
Trap instruction*
Exception Types and Priority
1
Section 4 Exception Handling
4
2
Start of Exception Handling
Starts immediately after a low-to-high transition at the RES
pin, or when the watchdog timer overflows. The CPU
enters the reset state when the RES pin is low.
Starts when execution of an illegal instruction code is
detected.
Starts when execution of the currently executed instruction
or exception handling ends, if the trace (T) bit in the EXR is
set to 1.
Starts when the direct transition occurs by execution of the
SLEEP instruction.
Starts when execution of the current instruction or
exception handling ends, if an interrupt request has been
issued. *
Started by execution of a trap instruction (TRAPA)
3
Section 4 Exception Handling
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